CACHE FLUSHING AND INVALIDATION

2.8 CACHE FLUSHING AND INVALIDATION

The MC88410 supports the ability to flush a single page or the entire cache while maintaining both vertical and horizontal cache coherency. It also allows for the incoherent invalidation of the cache. Flush page and flush all are coherent operations that cause the MC88410 to execute copyback transactions and primary cache invalidate transactions as needed. For the invalidate all operation, the MC88410 simply clears all the V bits in theMTAG and all the I bits in the PTAG. During a flush operation, the MC88410 is available for snooping and to process additional MC88110 transactions. However, during an invalidate operation, snooping is disabled and MC88110 transactions are stalled.

The flush page, flush all, and invalidate all operations begin at the lowest address in the selected granularity regardless of the actual address that was used. For example, flush all and invalidate all operations begin at tag location zero and increments up to the maximum tag address. A flush page begins at set zero for the selected page address and steps up to the maximum tag address for that page.

The following paragraphs describe the flush control signals, flush operations, and invalidate operations.

2.8.1 Flush and Invalidate Control

The MC88410 system interface has two flush control input signals: ^FO and ^Fl. It also includes the FBSY output signal to indicate when a flush or invalidate is in progress. The MC88410 initiates the flush and invalidate operations when it detects the appropriate encoding of flush control signals for at least one clock cycle. For the flush page operation, the MC88410 uses the page specified by the last cache-inhibited write before the flush control signals are detected (see 2.8.2 Flush Page and Flush All Operations for more information). The encoding for ^Fl and ^FO is shown in Table 2-7.

Table 2-7. Flush Control Signal Encoding

F1 FO Function

0 0 No operation 0 1 Flush page 1 0 Flush all 1 1 Invalidate all

To initiate a flush or invalidate operation, the appropriate flush control signals must be asserted for one clock cycle. When the MC88410 recognizes the flush control signal encoding, it asserts the FBSY signal one clock later and begins the flush or invalidate operation. Once one of the three operations has been initiated, the flush control signals are not sampled again by the MC88410 until the current operation completes and the signals are restored· to the no operation state. When the flush or invalidate operation has completed, the MC88410 negates the FBSY signal. The FBSY signal may be used to clear the external control register that drives the flush control signals.

Figure 2-19 shows the hardware required for one possible method for controlling the flush and invalidate mechanism. This illustration shows a control register and an address decoder added to the basic MC88110/M:88410 configuration. To initiate a flush or invalidate operation, the MC88110 performs a cache-inhibited write to the address of the control register. The data for this transaction is then latched into the control register, which asserts the appropriate flush control signals. The address of the control register must be encoded in address bits 31-20, because the lower 20 bits of the address are required to specify a page for the flush page operation.

hldress Control

Data

Figure 2·19. Flush Control Hardware

To Sfstem Memory

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2.8.2 Flush Page and Flush All Operations

The flush page and flush all operations are coherent operations that cause the MC88410 to execute copybacks and primary cache invalidations as needed. The flow for the flush operations is shown in Figure 2-20. When the flush control signals indicate that a flush operation should occur, the MC88410 asserts FBSY and starts at the lowest address of the cache or of the specific page in the cache. For each MTAG entry, both the MTAG and the PTAG are checked. If the MTAG entry indicates that the line is unmodified, no action needs to be taken, the address is incremented, and the next MT AG entry can be checked . If the MTAG entry indicates that the line is modified, the MC88410 must copy back the most recent copy of that line to main m.emory. If there is a hit in the PT AG with the inclusion bit set, the MC88410 must perform a primary cache invalidate transaction to determine whether the MC88110 has the most recent copy of the line. For more information about the primary cache invalidate transaction, see Section 4 Processor Bus Interface. If the MC88110 has a version of the line that is modified with respect to the secondary cache line, it performs a snoop copyback, the secondary cache is updated, and the inclusion bit of the PTAG entry is cleared. Once the MC88410 has ensured that it has the most recent copy of the cache line, it perfor?ls a copyback to main memory, clears the modified bit in the MTAG entry, and goes on to the next line.

To initiate a flush operation, the MC88110 can perform a cache-inhibited write to a control register on the system bus. The address is decoded as shown in Figure 2-21. Address bits 31-20 are used for the control register decoder, and address bits 19-0 specify the page to be flushed. The data for the cache-inhibited write transaction is latched into the control register and sets the flush co~trol pins to the flush page encoding. When the MC88410 recognizes the flush page encoding on the flush control signals, it asserts FBSY and begins the flush.

Note that for the flush page operation, the lower 20 bits of the 32-bit address is needed to specify the page to be flushed. Since the page address issued by the MC88110 occupies the lower three bits of the address bus, the misaligned access exception of the MC88110 must be disabled by setting the MXM bit in the processor status register of the MC88110.

When a misaligned access is attempted with the MXM bit set, the processor asserts the full misaligned address on the address bus, but performs the access to the next lower properly aligned boundary.

When initiating a flush page operation, the system must be careful to ensure that the proper page address is latched in the MC88410 when it recognizes the flush page encoding. Each time the MC88410 sees a cache-inhibited write on the processor bus, it latches the page address into the flush counter. The write is then propagated through the MC88410 and onto the system bus. When the write transaction is complete, the MC88110 is free to initiate another transaction. It is possible for the system to assert S_TA before the cache-inhibited write transaction has modified the control register, thus asserting the flush control signals. The MC88110 must not initiate another cache-inhibited write transaction to the MC88410 before the MC88410 recognizes the flush page encoding on the flush control signals and initiates the flush.

More Lines

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PTAG Hit Last Line

~ Not Asserted

Figure 2·20. Flush Operation Transaction Flow

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Otherwise, a new address is latched into the flush counter, and when the MC88410 recognizes the flush page encoding, it begins the flush operation to the wrong page. Since . the page address is ignored for the flush all operation, it is not necessary for the MC88110

to avoid all cache-inhibited write transactions before the flush all begins.

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