Operand Conventions

This section describes the operand conventions as they are represented in two levels of the PowerPC architecture. ^It also provides detailed descriptions of conventions used for storing values in registers and memory, accessing the 603e's registers, and representation of data in these registers.

Chapter 2. PowerPC 603e Microprocessor Programming Model 2-11

2.2.1 Floating-Point Execution Models-UISA

The IEEE 754 standard includes 64- and 32-bit arithmetic. The standard requires that single-precision arithmetic be provided for single-precision operands. The standard permits precision arithmetic instructions to have either (or both) single-precision or double-precision operands, but states that single-double-precision arithmetic instructions should not accept double-precision operands.

The PowerPC UISA follows these guidelines:

• Double-precision arithmetic instructions may have single-precision operands but always produce double-precision results.

• Single-precision arithmetic instructions require all operands to be single-precision and always produce single-precision results.

For arithmetic instructions, conversions from double- to single-precision must be done explicitly by software, while conversions from single- to double-precision are done implicitly.

All PowerPC implementations provide the equivalent of the following execution models to ensure that identical results are obtained. The definition of the arithmetic instructions for infinities, denormalized numbers, and NaNs follow conventions described in the following sections.

Although the double-precision format specifies an II-bit exponent, exponent arithmetic uses two additional bit positions to avoid potential transient overflow conditions. An extra bit is required when denormalized double-precision numbers are prenormalized. A second bit is required to permit computation of the adjusted exponent value in the following examples when the corresponding exception enable bit is 1:

• Underflow during multiplication using a denormalized factor

• Overflow during division using a denormalized divisor

2.2.2 Data Organization in Memory and Data Transfers

Bytes in memory are numbered consecutively starting with O. Each number is the address of the corresponding byte.

Memory operands may be bytes, half words, words, or double words, or, for the load/store multiple and move assist instructions, a sequence of bytes or words. The address of a memory operand is the address of its first byte (that is, of its lowest-numbered byte).

Operand length is implicit for each instruction.

2.2.3 Alignment and Misaligned Accesses

The operand of a single-register memory access instruction has a natural alignment boundary equal to the operand length. In other words, the "natural" address of an operand is an integral multiple of the operand length. A memory operand is said to be aligned if it is aligned at its natural boundary; otherwise it is misaligned.

2-12 PowerPC 603e RISC Microprocessor User's Manual

Operands for single-register memory access instructions have the characteristics shown in Table 2-8. (Although not permitted as memory operands, quad words are shown because quad-word alignment is desirable for certain memory operands.)

Table 2-8. Memory Operands

Operand Length Addr[28-31)

If Aligned

Byte 8 bits xxxx

Hall word 2 bytes xxxO

Word 4 bytes xxOO

Double word 8 bytes xOOO

Quad word 16 bytes 0000

Note: An "x· in an address bit position indicates that the bit can be 0 or 1 independent of the state 01 other bits in the address.

The concept of alignment is also applied more generally to data in memory. For example, a 12-byte data item is said to be word-aligned if its address is a multiple of four.

Implementation Notes-The following describes how the 603e handles alignment and misaligned accesses:

• The 603e provides hardware support for some misaligned memory accesses.

However, misaligned accesses will suffer a performance degradation compared to aligned accesses of the same type.

• The 603e does not provide hardware support for floating-point load/store operations that are not word-aligned. In such a case, the 603e will invoke an alignment exception and the exception handler must break up the misaligned access. For this reason, floating-point single- and double-word accesses should always be word-aligned. Note that a floating-point double-word access on a word-aligned boundary requires an extra cycle to complete.

Any memory access that crosses an alignment boundary must be broken into multiple discrete accesses. This includes half-word, word, double-word, and string references. For the case of string accesses, the hardware makes no attempt to get aligned in an effort to reduce the number of discrete accesses. (Multi word accesses are architecturally required to be aligned.) The resulting performance degradation depends upon how well each individual access behaves with respect to the memory hierarchy. At a minimum, additional cache access cycles are required. More dramatically, for the case of access to a noncacheable page, each discrete access involves an individual bus operation which will reduce the effective bandwidth of the bus.

The frequent use of misaligned accesses is discouraged since they can compromise the overall performance of the processor.

Chapter 2. PowerPC S03e Microprocessor Programming Model 2-13

2.2.4 Floating-Point Operand

The 603e provides hardware support for all single- and double-precision floating-point operations for most value representations and all rounding modes. The PowerPC architecture provides for hardware to implement a floating-point system as defined in ANSIIIEEE standard 754-1985, IEEE Standard for Binary Floating Point Arithmetic. For detailed information about the floating-point execution model refer to Chapter 3, "Operand Conventions," in The Programming Environments Manual.

2.2.5 Effect of Operand Placement on Performance

The VEA states that the placement (location and alignment) of operands in memory affect the relative performance of memory accesses. The best performance is guaranteed if memory operands are aligned on natural boundaries. To obtain the best performance from the 603e, the programmer should assume the performance model described in Chapter 3,

"Operand Conventions," in The Programming Environments Manual.