BIU H I-Cache II D-Cache II D-Cache II D-Cache .11 D-Cache I
3.10 MEl State Transactions
Table 3-8 shows MEl state transitions for various operations. Bus operations are described in Table 3-6.
Table 3-8. MEl State Transitions
Operation Cache Bus
WIM Current Next Cache Actions Bus
Operation sync State State Operation
Load Read No xOx I Same 1 Cast out of modified Write-with-kill
(T =0) block (as required)
2 Pass four-beat read Read to memory queue
Load Read No xOx E,M Same Read data from cache
-(T = 0)
Load (T =0) Read No xlx I Same Pass single-beat read Read
to memory queue
Load (T = 0) Read No xlx E I CRTRY read
-Load (T = 0) Read No xlx M I CRTRY read (push Write-with-kill
sector to write queue) Iwarx Read Acts like other reads but bus operation uses special encoding
Store Write No OOx I Same 1 Cast out of modified Write-with-kill
(T =0) block (if necessary)
2 Pass RWITM to RWITM memory queue
Store Write No OOx E,M M Write data to cache
-(T = 0)
Store", stwcx. Write No lOx I Same Pass single-beat write
Write-with-(T = 0) to memory queue flush
Store", stwcx. Write No lOx E Same 1 Write data to cache
-(T = 0)
2 Pass single-beat Write-with-write to memory flush queue
Store", stwcx. Write No lOx M E 1 CRTRYwrite
-(T = 0)
2 Push block to write Write-with-kill queue
Store (T = 0) Write No xlx I Same Pass single-beat write
Write-with-orstwcx. to memory queue flush
(WIM= lOx)
Store (T = 0) Write No xlx E I CRTRYwrite
-orstwcx.
(WIM = lOx)
3-28 PowerPC 603e RISC Microprocessor User's Manual
Table 3-8. MEl State Transitions (Continued)
Operation Cache Bus
WIM Current Next
Cache Actions Bus
Operation sync State State Operation
Store (T = 0) Write No x1x M I 1 CRTRYwrite
-oratwcx.
(WIM= 10x) 2 Push block to write Write·with-kill
queue
atwcL Conditional If the reserved bit is set, this operation is like other writes except the bus operation write uses a special encoding.
dcbf Data cache No xxx I,E Same 1 CRTRYdcbf
zero 2 Cast out of modified Write-with-kill
block
block touch to memory queue
dcbt Data cache No x1x E I CRTRYread
-block touch
dcbt Data cache No x1x M I 1 CRTRYread
-block touch
2 Push block to write Write-with-kill queue
Chapter 3. Instruction and Data Cache Operation 3-29
Table 3-8. MEl State Transitions (Continued)
Operation Cache Bus
WIM Current Next Cache Actions Bus
Operation sync State State Operation
dcbt Oatacache No xOx I Same 1 Cast out of modified Write-with-kill
block touch block (as required)
2 ' Pass four-beat read Read to memory queue
dcbt Oatacache No xOx E,M Same No aetion
-blc>cktouch
Single-beat Reload No xxx I Same Forward data_in
-read dump 1
Four-beat read Reload No xxx I E Write data_in to cache
-(double-word- dump aligned)
Four-beat write Reload No xxx I M Write datajn to cache
-(double-word- dump aligned)
E-+I Snoop No xxx E I State change only
-write or kill (committed)
M-+I Snoop No xxx M I State change only
-kill (committed)
Push Snoop No xxx M I Conditionally push Write-with-kill
M-+I flush
Push Snoop No xxx M E Conditionally push Write-with-kill
M-+E clean
tlble TLB No xxx x x 1 CRTRYTLBI
-invalidate
2 PassTLBI
-3, Noaetion
-sync Synchroni- No xxx x x 1 CRTRYsync
-zalion
2 Pass sync
-: 3 Noaetion
-Note that single-beat writes are not snooped in the write queue.
3-30 PowerPC 6038 RISC Microprocessor User's Manual
Chapter 4 Exceptions
The PowerPC exception mechanism allows the processor to change to supervisor state (referred to as privileged state in the architecture specification) as a result of external signals, errors, or unusual conditions arising in the execution of instructions. When exceptions (referred to as interrupts in the architecture specification) occur, information about the state of the processor is saved to certain registers and the processor begins execution at an address (exception vector) predetermined for each exception. Processing of exceptions occurs in supervisor mode.
Although multiple exception conditions can map to a single exception vector, a more specific condition may be determined by examining a register associated with the exception-for example, the DSISR or the FPSCR. Additionally, certain exception conditions can be explicitly enabled or disabled by software.
The PowerPC architecture requires that exceptions be handled in program order; therefore, although a particular implementation may recognize exception conditions out of order, they are handled strictly in order with respect to the instruction stream. When an instruction-caused exception is recognized, any unexecuted instructions that appear earlier in the instruction stream, including any that have not yet entered the execute state, are required to complete before· the exception is taken. An instruction is said to have "completed" when the results of that instruction's execution have been committed to the registers defined by the architecture (for example, the GPRs or FPRs, rather than rename buffers). If a single instruction encounters multiple exception conditions, those exceptions are taken and handled sequentially. Likewise, exceptions that are asynchronous are recognized when they occur, but are not handled until the next instruction to complete in program order successfully completes. Throughout this chapter, the term "next instruction" implies the next instruction to complete in program order.
Note that exceptions can occur while an exception handler routine is executing, and multiple exceptions can become nested. It is up to the exception handler to save the states to allow control to ultimately return to the original excepting program.
Chapter 4. Exceptions 4-1
In many cases, after an exception handler handles an exception, there is an attempt to execute the instruction that caused the exception. Instruction execution continues until the next exception condition is encountered. This method of recognizing and handling exception conditions sequentially guarantees that the machine state is recoverable and processing can resume without losing instruction results.
Exception handlers should save the information stored in SRRO and SRRI soon after the exception is taken to prevent this information from being lost due to another exception being taken. The' information should be saved before enabling any exception that is automatically disabled when an exception is taken.
In this chapter, the following terminology is used to describe the various stages of exception processing:
Recognition Exception recognition occurs when the condition that can cause an exception is identified by the processor.
Taken An exception is said to be taken when control of instruction execution is passed to the exception handler; that is, the context is saved and the instruction at the appropriate vector offset is fetched and the exception handler routing is executed in sup,ervisor mode.
Handling Exception handling is performed by the software linked to the appropriate vector offset. Exception handling is performed at supervisor-level.