External Interrupt (Ox00500)

An external interrupt is signaled to the 603e by the assertion of the INT signal as described in Section 7.2.9.1, "Interrupt (INn-Input." The interrupt may not be recognized if a higher priority exception occurs simultaneously or if the MSR[EE] bit is cleared when INT is asserted.

After the INT is detected (and provided that MSR[EE] is set), the 603e generates a recoverable halt to instruction completion. The. 603e requires the next instruction in program order to complete or except, block completion of any following instructions, and allow the completed store queue to drain. If any other exceptions are encountered in this process, they are taken first and the external interrupt is delayed until a recoverable halt is achieved. At this time the 603e saves the state information and takes the external interrupt as defined in the PowerPC architecture.

The register settings for the external interrupt are shown in Table 4-13.

Chapter 4. Exceptions 4-25

Table 4-13. External Interrupt-Register Settings

Register Setting

SRRa Set to the effective address of the instruction that the processor would have attempted to execute next if no interrupt conditions were present.

SRR1 ()""15 Cleared

16-31 Loaded from bits 16-31 of the MSR

MSR POW a EE a FEa a IR a

rGPRa PR a SE a DR a

ILE

-

IP

-

^-

When an external interrupt is taken, instruction execution for the handler begins at offset Ox00500 from the physical base address indicated by MSR[IP].

The 603e only recognizes the interrupt condition (INT asserted) if the MSR[EE] bit is set;

it ignores the interrupt condition if the MSR[EE] bit is cleared. To guarantee that the external interrupt is taken, the INT signal must be held active until the 603e takes the interrupt. If the INT signal is negated before the interrupt is taken, the 603e is not guaranteed to take an external interrupt. The interrupt handler must send a command to the device that asserted INT, acknowledging the interrupt and instructing the device to negate INT.

4.5.S Alignment Exception (OxOOSOO)

This section describes conditions that can cause alignment exceptions in the 603e. Similar to DSI exceptions, alignment exceptions use the SRRO and SRRI to save the machine state and the DSISR to determine the source of the exception. The 603e will initiate an alignment exception when it detects any of the following conditions:

• The operand of a floating-point load or store operation is not word-aligned.

• The operand of an Imw, stmw, Iwarx, or stwcx. instruction is not word-aligned.

• A little-endianaccess (MSR[LE] = 1) is misaligned.

• A multiple or string access is attempted with the MSR[LE] bit set.

• The operand of a dcbz instruction is in a page that is write-through or caching-inhibited.

The register settings for alignment exceptions are shown in Table 4-13.

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Table 4-14. Alignment Interrupt-Register Settings

Register Setting

SRRO Set to the effective address of the instruction that caused the exception.

SRR1 0-15 Cleared

16-31 Loaded from bits 16--31 of the MSR

MSR POW 0 EE 0 FEO 0 IR 0

TGPRO PR 0 SE 0 DR 0

ILE

-

IP - ME

-

DSISR 0-11 Cleared

12-13 Cleared. (Note that these bits can be set by several 64-bit PowerPC instructions that are not supported in the 603e.)

14 Cleared

15-16 For instructions that use register indirect with index addressing-set to bits 29-30 of the instruction.

For instructions that use register indirect with immediate index addressing--cleared.

17 For instructions that use register indirect with index addressing-set to bit 25 of the instruction.

For instructions that use register indirect with immediate index addressing- Set to bit 5 of the instruction

18-21 For instructions that use register indirect with index addressing-set to bits 21-24 of the instruction.

For instructions that use register indirect with immediate index addressing-set to bits 1-4 of the instruction.

22-26 Set to bits 6--10 (identifying either the source or destination) of the instruction. Undefined for dcbz.

27-31 Set to bits 11-15 of the instruction (rA)

Set to either bits 11-15 of the instruction or to any register number not in the range of registers loaded by a valid form instruction, for Imw, Iswi, and Iswx instructions.

Otherwise undefined.

DAR Set to the EA of the data access as computed by the instruction causing the alignment exception.

The architecture does not support the use of an unaligned EA by Iwarx or stwcx.

instructions. If one of these instructions specifies an unaligned EA, the exception handler should not emulate the instruction, but should treat the occurrence as a programming error.

4.5.6.1 Integer Alignment Exceptions

The 603e is optimized for load and store operations that are aligned on natural boundaries.

Operations that are not naturally aligned may suffer performance degradation, depending on the type of operation, the boundaries crossed, and the mode that the processor is in during execution. More specifically, these operations may either cause an alignment exception or they may cause the processor to break the memory access into multiple, smaller accesses with respect to the cache and the memory subsystem.

Chapter 4. Exceptions 4-27

The 603e can initiate an alignment exception for the access shown in Table 4-15. In this cases, the appropriate range check is performed before the instruction begins execution. As a result, if an alignment exception is taken, it is guaranteed that no portion of the instruction has been executed.

Table 4-15. Access Types

MSR[DR) SR[T] Access Type

1 0 Page-address translation access

4.5.6.1.1 Page Address Translation Access

A page-address translation access occurs when MSR[DR] is set, SR[T] is cleared and there is not a match in the BAT. Note the following points:

• The following is true for all loads and stores except strings/multiples:

- Byte operands never cause an alignment exception.

- Half-word operands can cause an alignment exception if the EA ends in OxFFF.

- Word operands can cause an alignment exception if the EAends in OxFFD-FFF.

- Double-word operands cause an alignment exception if the EA ends in OxFF9-FFF.

• The dcbz instruction causes an alignment exception if the access is to a page or block with the W (write-through) or I (cache-inhibit) bit set in the TLB or BAT, respectively.

A misaligned memory access that does not cause an alignment exception will not perform as well as an aligned access of the same type. The resulting performance degradation due to misaligned accesses depends on how well each individual access behaves with respect to the memory hierarchy. At a minimum, additional cache access cycles are required that can delay other processor resources from using the cache. More dramatically, for an access to. a noncacheable page, each discrete access involves individual processor bus operations that reduce the effective bandwidth of that bus.

Finally, note that when the 603e is in page address translation mode, there is no special handling for accesses that fall into BAT regions.

4.5.6.2 Floating-Point Alignment Exceptions

The 603e implements the alignment exception as it is defined in the PowerPC architecture.

For information on bit settings and how exception conditions are detected, refer to The Programming Environments Manual.

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Note that the PowerPC architecture allows individual processors to determine whether an exception is required to handle various alignment conditions. The 603e initiates an alignment exception when it detects any of the following conditions:

• The operand of a floating-point load or store operation is not word-aligned.

• The operand of a dcbz instruction is in a page that is write-through or caching-inhibited for a virtual mode access.

• The operand of an Imw, stmw, Iwarx, or stwcx. instruction is not word-aligned.

Note that unlike other alignment exceptions, which store the address as computed by the instruction in the DAR, alignment exceptions for load or store multiple instructions store that address value + 4 into the DAR.

• A little-endian access is misaligned.

• A multiple access is attempted while the little-endian, MSR[LE], bit is set.