BIU H I-Cache II D-Cache II D-Cache II D-Cache .11 D-Cache I
4.5. S Floating-Point Unavailable Exception (OxOOSOO)
4.5.14 Data TLB Miss on Store Exception (Ox01200)
When the effective address for a data store or cache operation cannot be translated by the DTLBs, a data TLB miss on store exception is generated. The data TLB miss on store exception is also taken when the changed bit (C
=
0) for a DTLB entry needs to be updated for a store operation. Register settings for the instruction and data TLB miss exceptions are described in Table 4-17.If a data TLB miss exception handler fails to find the desired PTE, then a page fault must be synthesized. The handler must restore the machine state and turn off the TGPRs before invoking a DSI exception (OxOO300).
Software table search operations are discussed in Chapter 5, "Memory Management."
When a data TLB miss on store exception is taken, instruction execution for the handler begins at offset Ox01200 from the physical base address indicated by MSR[IP].
4.5.15 Instruction Address Breakpoint Exception (Ox01300)
The instruction address breakpoint is controlled by the IABR special purpose register.
IABR[0-29] holds an effective address to which each instruction is compared. The exception is enabled by setting IABR[30]. Note that the 603e ignores the translation enable bit (IABR[31]). The exception is taken when an instruction breakpoint address matches on the next instruction to complete. The instruction tagged with the match is not completed before the instruction address breakpoint exception is taken.
The breakpoint action can be one of the following:
• Trap to interrupt vector Ox01300 (default)
• Soft stop
The bit settings for when an instruction address breakpoint exception is taken are shown in Table 4-18.
Table 4-18. Instruction Address Breakpoint Exception-Register Settings
Register Setting Description
SRRa Set to the address of the next instruction to be executed in the program for which the TLB miss exception was generated.
SRR1 0-15 Cleared
16-31 Loaded from bits 16-31 olthe MSR
MSR POW a EE a FEa a IR a
TGPRa PR a SE a DR a
ILE - FP a BE a RI a
IP - ME
-
FE1 a LE Set to value of ILEThe default breakpoint action is to trap before the execution of the matching instruction.
Chapter 4. Exceptions 4-35
The soft stop feature can be enabled onIy through the COP interface. With soft stop enabled, the 603e stops in a restartable state, while with hard stop enabled, the 603e stops immediately without attempting to reach a restrutable state. Upon restarting from a soft stop, the matching instructions are executed and' completed unless it generates an exception. For soft stops, the next ten instructions that could have passed the IABR check can be monitored only by single-stepping the processor. When soft stops are used, the address compare must be separated by at least 10 instructions.
If soft stop is enabled, only one soft stop is generated before completion of an instruction with an IABR match, regardless of whether a soft stop i~ generated before that instruction for any other reason, such as trace mode on for the preceding instruction or a COP soft stop request.
Table 4-19 shows the priority of actions taken when more than one mode is enabled for the same instruction.
Table 4-19. Breakpoint Action for Multiple Modes Enabled for the Same Address
IABR[IE] MSR[BE] MSR[SE] First Action Next Action Comments
1 1 0 Instruction Trace Enabling both modes is useful only if both address (branch) trace and address breakpoint interrupts
are needed.
1 0 1 Instruction Trace Enabling both modes is useful only if address (single-step) different breakpoint actions are required.
breakpoint
0 1 1 Trace None The action for branch trace and Single-step (branch) trace is the same. Enabling both trace
modes is redundant except for hard stop on branches.
1 1 1 Instruction Trace Enabling all modes is redundant. This address entry is for clarification only.
breakpoint
Note that a trace or instruction address breakpoint exception condition generates a soft stop instead of an exception if soft stop has been enabled by the JTAG/COP logic. If trace and breakpoint conditions occur simultaneously, the breakpoint conditions receive higher priority.
The 603e requires that an mtspr instruction that updates the IABR be followed by a context-synchronizing instruction. If the mtspr instruction enables the instruction address breakpoint exception, the context-synchronizing instruction cannot generate a breakpoint response. The 603e also cannot block a breakpoint response on the context-synchronizing instruction if the breakpoint was disabled by the mtspr instruction. See "Synchronization Requirements for Special Registers and TLBs" in Chapter 2, "Register Set," in The Programming Environments Manual" for more information on this requirement.
4-36 PowerPC 603e RISC Microprocessor User's Manual
4.5.16 System Management Interrupt (Ox01400)
The system management interrupt behaves like an external interrupt except for the signal asserted and the vector taken. A system management interrupt is signaled to the 603e by the assertion of the SMI signal. The interrupt may not be recognized if a higher priority exception occurs simultaneously or if the MSR[EE] bit is cleared when SMI is asserted.
Note that SMI takes priority over INT if they are recognized simultaneously.
After the SMI is detected (and provided that MSR[EE] is set), the 603e generates a recoverable halt to instruction completion. The 603e requires the next instruction in program order to complete or except, block completion of any following instructions, and allow the completed store queue to drain. If any higher priority exceptions are encountered in this process, they are taken first and the system management interrupt is delayed until a recoverable halt is achieved. At this time the 603e saves state information and takes the system management interrupt.
The register settings for the external interrupt exception are shown in Table 4-20.
Table 4-20. System Management Interrupt-Register Settings
Register Setting Description
SRRa Set to the effective address of the instruction that the processor would have attempted to complete next if no interrupt conditions were present.
SRR1 0-15 Cleared
16-31 Loaded from bits 16-31 of the MSR
MSR POW a EE a FEa a IR a
TGPRa PR a SE a DR a
ILE
-
FP a BE a RI aIP - ME
-
FE1 a LE Set to value of ILEWhen a system management interrupt is taken, instruction execution for the handler begins at offset Ox01400 from the physical base address indicated by MSR[lP].
The 603e recognizes the interrupt condition (SMI asserted) only if the MSR[EE] bit is set;
and ignores the interrupt condition otherwise. To guarantee that the external interrupt is taken, the SMI signal must be held active until the 603e takes the interrupt. If the SMI signal is negated before the interrupt is taken, the 603e is not guaranteed to take a system management interrupt. The interrupt handler must send a command to the device that asserted SMI, acknowledging the interrupt and instructing the device to negate SMI.
Chapter 4. Exceptions 4·37