Cache Control Instructions

Software must use the appropriate cache management instructions to ensure that caches are kept consistent when data is modified by the processor. When a processor alters a memory location that may be contained in an instruction cache, software must ensure that updates to memory are visible to the instruction fetching mechanism. Although the instructions to enforce coherency vary among implementations and hence operating systems should provide a system service for this function, the following sequence is typical:

I. debst (update memory) 2. syne (wait for update)

3. icbi (invalidate copy in. cache)

4. isyne (invalidate copy in own instruction buffer)

These operations are necessary because the processor does not maintain instruction memory coherent with data memory. Software is responsible for enforcing coherency of instruction caches and data memory. Since instruction fetching may bypass the data cache, changes made to items in the data cache may not be reflected in memory until after the instruction fetch completes.

The PowerPC architecture defines instructions for controlling both the instruction and data caches when they exist. The 603e interprets the cache control instructions (icbi, debi, debt, debz, debst)as if they pertain only to the 603e's caches. They are not intended for use in managing other caches in the system.

The debz instruction causes an address-only broadcast on the bus if the contents of the block are from a page marked global through the WIMG bits. This broadcast is performed for coherency reasons; the debz instruction is the only cache control instruction that can allocate and take new ownership of a line. The other instructions do not broadcast either for the purpose of invalidating or flushing other caches in the system or for managing system resources. Any bus activity caused by these instructions is the direct result of performing the operation in the 603e cache. Note that a data access exception is generated if the effective address of a debi, debst, debf, or debz instruction cannot be translated due to the lack of a TLB entry. Note that exceptions are referred to as interrupts in the architecture specification.

Note that in the PowerPC architecture, the term cache block, or simply block when used in the context of cache implementations, refers to the unit of memory at which. coherency is maintained. For the 603e this is the eight-word cache line. This value may be different for other PowerPC implementations. In-depth descriptions of coding these instructions is provided in Chapter 3, "Addressing Modes and Instruction Set Summary," and Chapter 10,

"Instruction Set," in The Programming Environments Manual.

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3.7.1 Data Cache Block Touch (dcbt) Instruction

This instruction provides a method for improving performance through the use of software-initiated prefetch hints. The 603e performs the fetch for the cases when the address hits in the TLB or the BAT registers, and when it is a permitted load access from the addressed page. The operation is treated similarly to a byte load operation with respect to coherency.

If the address translation does not hit in the TLB or BAT mechanism, or if it does not have load access permission, the instruction is treated as a no-op.

If the cache is locked or disabled, or if the access is to a page that is marked as guarded, the debt instruction is treated as a no-op.

If the access is directed to a write-through or caching-inhibited page, the instruction is treated as a no-op.

The debt instruction never affects the referenced or changed bits in the hashed page table.

A successful debt instruction affects the state of the TLB and cache LRU bits as defined by the LRU algorithm.

The touch load buffer will be marked invalid if the contents of the touch buffer have been moved to the cache, if any data cache management instruction has been executed, if a debz instruction is executed that matches the address of the cache block in the touch buffer, or if another debt instruction is executed.

3.7.2 Data Cache Block Touch for Store (dcbtst) Instruction

The debtst instruction, like the data cache block touch instruction (debt), allows software to prefetch a cache block in anticipation of a store operation (read with intent to modify).

3.7.3 Data Cache Block Clear to Zero (dcbz).Instruction

If the block containing the byte addressed by the EA is in the data cache, all bytes are cleared.

If the block containing the byte addressed by the EA is not in the data cache and the corresponding page is caching-allowed, the block is established in the data cache without fetching the block from main memory, and all bytes of the block are cleared. If the contents of the cache block are from a page marked global through the WIM bits, an address-only bus transaction is run.

If the page containing the byte addressed by the EA is caching-inhibited or write-through, then the system alignment exception handler is invoked.

The debz instruction is treated as a store to the addressed byte with respect to address translation and protection.

Chapter 3. Instruction and Data Cache Operation 3-23

3.7.4 Data Cache Block Store (dcbst) Instruction

Ifthe block containing the byte addressed by the EA is in coherence required mode, and a block containing the byte addressed by the EA is in the data cache of any processor and has been modified, the writing of it to main memory is initiated.

The function of this instruction is independent of the write-through and caching-inhibited/caching-allowed modes of the blOCk containing the byte addressed by the EA.

This instruction is treated as a load to the addressed byte with respect to address translation and protection.

3.7.5 Data Cache Block Flush (dcbf) Instruction

The action taken depends on the memory mode associated with the target, and on the state of the cache block. The list below describes the action taken for the various cases. The actions described are executed regardless of whether the page containing the addressed byte is in caching-inhibited or caching-allowed mode. The following actions occur in both coherency-required mode (WIM

=

=

ObXXO).

The debf instruction causes the following cache activity:

• Unmodified block-Invalidates the block in the processor's cache.

• Modified block-Copies the block to memory and invalidates data cache block.

• Absent block-Does nothing.

The 603e treats this instruction as a load to the addressed byte with respect to address translation and protection.

3.7.6 Enforce In-Order Execution of I/O Instruction (eieio)

As defined by the PowerPC architecture, the eieioinstruction provides an ordering function for the effects of load and store instructions executed by a given processor. Executing eieio ensures that all memory accesses previously initiated by the given processor are completed with respect to main memory before any memory acces~es subsequently initiated by the processor access main memory. The eieio instruction orders loads and stores to caching-inhibited memory only.

The eieio instruction is intended for use only in performing memory-mapped 110 operations. It enforces "strong" ordering of cache-inhibited memory accesses during 110 operations between the processor and 110 devices.

When executed by the 603e, the eieio instruction is treated as a no-op; caching-inhibited load and store operations (inhibited by the WIMG bits for the page) are performed in strict program order.

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3.7.7 Instruction Cache Block Invalidate (icbi) Instruction

The execution of an icbi instruction causes all four cache sets indexed by the EA to be marked invalid. No cache hit is required, and no MMU translation is performed.

3.7.8 Instruction Synchronize (isync) Instruction

The isync instruction waits for all previous instructions to complete and then discards any previously fetched instructions, causing subsequent instructions to be fetched (or refetched) from memory and to execute in the context established by the previous