Other Functional Descriptions

Entering and Exiting Hold Acknowledge

The Bus Hold Acknowledge State, Th, is entered in response to the HOLD input being asserted. In the Bus Hold Acknowledge state, the Am386DXlDXL microprocessor floats all output or bidirectional signals, except for HLDA. HLDA is asserted as long as the

Am386DXlDXL CPU remains in the bus hold acknowl-edge state. In the Bus Hold Acknowlacknowl-edge state, all in-puts except HOLD, FL T, RESET, BUSY, ERROR, and PEREQ are ignored (also up to one rising edge on NMI is remembered for processing when HOLD is no longer asserted).

1

^Idle

1'-

Acknowledge - - . Hold

1

^Idle

1

Ti Th Th Th Ti

ClK2

[

(ClK)

[

HOLD

[

HlDA

[

BE3-BEO,

[

A31-A2, M/iO,

\

--Tlo·;"r--Die, W/R

ADS

[

' _ . (Floating) . _ -NA

[

8S16

[

READY

[

(Floating)

-I -I

[ - - - - - - -

{Floating)---I I

D31-DO

Note: For maximum design flexibility, the Am386DXlDXL CPU has no internal pullup resistors on its outputs. The design may require an external pullup on ADS and other Am386DX/DXL CPU outputs to keep them negated during float periods.

Figure 64. Requesting Hold from Idle Bus Am386DXlDXL Microprocessor Data Sheet

150218-067

99

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Th may be entered from a bus idle state, as in Figure 64, or after the acknowledgment ofthe current physical bus cycle if the LOCK signal is not asserted, as in Figures 65 and 66. If HOLD is asserted during a locked bus cycle, the Am386DXlDXL microprocessor may execute one unlocked bus cycle before acknowledging HOLD. If as-serting B816 requires a second 16-bit bus cycle to com-plete a physical operand transfer, it is performed before HOLD is acknowledged, although the bus state dia-grams in Figures 53 and 59 do not indicate that detail.

Th is exited in response to the HOLD input being ne-gated. The following state will be Ti as in Figure 64 if no bus request is pending. The following bus state will be T1 if a bus request is internally pending, as in Figures 65 and 66.

Th is also exited in response to RESET being asserted.

If a rising edge occurs on the edge-triggered NMI in-put while in Th, the event is remembered as a non-maskable interrupt 2 and is serviced when Th is exited, unless of course, the Am386DXlDXL microprocessor is reset before Th is exited.

RESET During HOLD Acknowledge

RESET being asserted takes priority over HOLD being asserted. Therefore, Th is exited in response to the RESET input being asserted. If RESET is asserted while HOLD remains asserted, the Am386DXlDXL mi-croprocessor drives its pins to defined states during reset, as in Table 15 Pin State During RESET, and performs internal reset activity as usual.

If HOLD remains asserted when RESET is negated, the Am386DXlDXL microprocessor enters the hold ac-knowledge state before performing its first bus cycle, provided HOLD is still asserted when the Am386DXI DXL microprocessor would otherwise perform its first bus cycle. If HOLD remains asserted when RESET is negated, the BUSY input is still sampled as usual to de-termine whether a self test is being requested, and ER-ROR is still sampled as usual to determine whether a 387DX math coprocessor versus an 80287 (or none) is present.

Float

Activating the FL T input floats all Am386DXlDXL CPU bidirectional and output signals, including HLDA. As-serting FL T isolates the Am386DXlDXL CPU from the surrounding circuitry.

As the Am386DXlDXL microprocessor is packaged in a surface mount PQFP, it cannot be removed from the motherboard when In-Circuit Emulation (ICE) is needed. The FL T input allows the Am386DXlDXL CPU to be electrically isolated from the surrounding circuitry.

This allows connection of an emulator to the Am386DXI DXL microprocessor PQFP without removing it from the PCB. This method of emulation is referred to as ON-Circuit Emulation (ONCE).

Entering and Exiting Float

FL T is an asynchronous, active Low input. It is recog-nized on the rising edge of CLK2. When recogrecog-nized, it aborts the current bus cycle and floats the outputs of the Am386DXlDXL microprocessor (Figure 68). FL T must be held Low for a minimum of 16-CLK2 cycles. Reset should be asserted and held asserted until after FL T is deasserted. This will ensure that the Am386DXlDXL CPU will exit Float in a valid state.

Asserting the FL T input unconditionally aborts the cur-rent bus cycle and forces the Am386DXlDXL micro-processor into the Float mode. Since activating FL T unconditionally forces the Am386DXlDXL CPU into Float mode, the Am386DXlDXL CPU is not guaranteed to enter Float in a valid state. After deactivating FL T, the Am386DXlDXL CPU is not guaranteed to exit Float mode in a valid state. This is not a problem, as the FL T pin is meant to be used only during ONC E. After exiting Float, the Am386DXlDXL CPU must be reset to return it to a valid state. Reset should be asserted before FL Tis deasserted. This will ensure that the Am386DXlDXL CPU will exit Float in a valid state.

FL T has an internal pull-up resistor, and if it is not used it should be unconnected.

Bus Activity During and Following Reset

RESET is the highest priority input signal capable of in-terrupting any processor activity when it is asserted. A bus cycle in progress can be aborted at any stage; or idle states or bus hold acknowledge states discontinued so that the RESET state is established.

RESET should remain asserted for at least 15-CLK2 periods to ensure it is recognized throughout the Am386DXlDXL microprocessor, and at least 80-CLK2 periods if Am386DXlDXL device self-test is going to be requested at the falling edge. RESET asserted pulses less than 15 CLK2 periods may not be recognized.

RESET pulses less than 80 CLK2 periods followed by a self-test may cause the self-test to report a failure when no true failure exists.

The additional RESET pulse width is required to clear additional state prior to valid self-test.

Provided the RESET falling edge meets setup and hold times, t25 and t26, the internal processor clock phase is defined at that time, as illustrated by Figure 67.

An Am386DXlDXL microprocessor self-test may be re-quested at the time RESET is negated by having the BUSY input at a Low level, as shown in Figure 67. The self-test requires (220) + approximately 60-CLK2 periods to complete. The self-test duration is not affected by the test results. Even if the self-test indicates a problem, the Am386DXlDXL device attempts to proceed with the re-set sequence afterward.

100 Am3S6 Microprocessors for Personal Computers

After the RESET falling edge (and after the self-test if it was requested) the Am386DXlDXL microprocessor performs an internal initialization sequence for approxi-mately 350 to 450 CLK2 periods.

The Am386DXlDXL microprocessor samples its ER-ROR input some time after the falling edge of RESET and before executing the first ESC instruction. During

ClK2

[

(ClK)

[

HOLD

[

HlDA

[

MriO, BE3-BEO,

[

A31-A2, Die, wrf5.

ADS

[

NA

[

BS16

[

LOCK [

031-00 [ -T1

Cycle 1 Non-Pipelined

(Read) T2

Valid 1

(Floating)

T2

---r---this sampling period BUSY must be High. If ERROR was sampled active, the Am386DXlDXL device em-ploys the 32-bit protocol of a 387DX math coprocessor.

Even though this protocol was selected, it is still neces-sary to use a software recognition test to determine the presence or identity of the coprocessor and to assure compatibility with future processors.

Hold Acknowledge

Th Th

>. ---- (~I~afti~!l)

-(Floating) In - - -

-Cycle 2 Non-Pipelined

(Write)

T1 T2

Valid 2

Valid 2

Out

Note: HOLD is a synchronous input and can be asserted at any CLK2 edge, provided setup and hold (t23 and t24) requirements are met. This waveform is useful for determining Hold Acknowledge latency.

150218-068

Figure 65. Requesting Hold from Active Bus (NA Negated)

Am386DXlDXL Microprocessor Data Sheet 101

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ClK2

[

(ClK)

[

HOLD

[

HlOA

[

MOO, SE3-SEO,

[

A31-A2, 010', WiFi ADS

[

NA

[

9816

[

READY

[

LOCK

[

031-00

T1P

Cycle 1 Pipelined

(Wr~e)

T21 T21

(Negated or last locked Cycle)

Hold Acknowledge

Th Th

(Floating)

---r---(Floating)

Valid 1

>. --- -(~I~fati~~)-

^{- -}

--,.._----tf----....I---tf---. (Floating) -

---'----+---r---r---'

Cycle 2 Non-Pipelined

(Read)

T1 T2

Valid 2

Valid 2

Note: HOLD is a synchronous input and can be asserted at any CLK2 edge, provided setup and hold (t23 and t24) requirements are met. This waveform is useful for determining Hold Acknowledge latency.

In

15021B-069 Figure 66. Requesting Hold from Active Bus (NA Asserted)

Table 21. Component and Revision Identifier History

Intel Am386DXlDXl Component Revision

i386 Microprocessor Identifier Identifier Stepping Name Revision

01 D ^{03 08}

102 Am386 Microprocessors for Personal Computers

II Reset ~ II

~ 15 ClK2 duration if not

Internal

Initialization Cycle 1

going to request self-test. Non-Pipelined

ClK2 Reset

ClK (Internal)

BUSY

ERROR BE3-BEO, W/f5..

Miio, HlOA

A31-A2, DIG, LOCK ADS

NA BS16 READY

[ [ [

[ [ [ [

[ [ [

~ 80 ClK2 duration before requesting self-test.

If self-test is performed, add (Read)

( (220 ) + 60' to these numbers T1 T2

1 2 3 17 18 19 395 396 397 398

031-00 [

XXXXXXX>- -- - -- ----

(Floating)' - - -- - - - -- -- - -- - - - --Notes: 1. BUSY should be held stable for 8-CLK2 periods before and after the CLK2 period in which RESET falling edge occurs.

2. If self-test is requested, the Am386DX/DXL microprocessor outputs remain in their reset state as shown here and in Table 14.

Figure 67. Bus Activity from Reset Until First Code Fetch 150218-070

CLK2 [

[~

I

[

=::X~=v:;:a:;:lid;::::::::;}:--

---'-- - - -

,'---..X'--Control

Data

[ --0 -<

^Valid )-- -- - -- - - - -- - -- - - -- - - -- -- --

< x=:

Address

[ ==><

V a l i d > - -- -- -- -- -- -- -- -- - -- -- - -- - --{\,..._--JX'-_ _

Reset [

---~I

150228-029 Figure 68. Entering and Exiting Fl T

Am386DXlDXl Microprocessor Data Sheet 103 ⁱ

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Dans le document Arn386 " Microprocessors for Personal Computers (Page 104-109)