Introduction
All data transfers occur as a result of one or more bus cycles. Logical data operands of byte, word, and Dword lengths may be transferred without restrictions on physical address alignment. Any byte boundary may be used, although two or even three physical bus cycles are performed as required for unaligned operand transfers. See Dynamic Data Bus Sizing and Operand Alignment.
The Am386DXlDXL microprocessor address signals are designed to simplify external system hardware.
Higher-order address bits are provided by A31-A2.
Lower-order address in the form of BE3-BEO directly provides linear selects for the four bytes of the 32-bit data bus. Physical operand size information is thereby implicitly provided for each bus cycle in the most usable form.
Byte Enable outputs, BE3-BEO, are asserted when their associated data bus bytes are involved with the present bus cycle, as listed in Table 17. During a bus cycle, any possible pattern of contiguous asserted Byte Enable outputs can occur, but never patterns having a negated Byte Enable separating two or three asserted Enables.
Address bits AO and A1 of the physical operand's base address can be created when necessary (for
L H
L x H L L L L x H L
L L x L H H x x H x L
L H L
BE1 K - Map for A 1 Signal
L H
L x L H L L
L x L H H L L x H H x x~ ~ L
L H L
BE1 K - Map for AO Signal
instance, for MUL TIBUS I or MUL TIBUS II interface), as a function of the lowest-order asserted Byte Enable.
This is shown by Table 18. Logic to generate AO and A 1 is given by Figure 43.
Table 17. Byte Enables and Associated Data and Operand Bytes Byte Enable Signal Associated Data Bus Signals
BEO 07-00 (Byte a-least significant)
BET 015-08 (Byte 1) BE2 023-016 (Byte 2)
BE3 D31-D24 (Byte 3-most significant) Each bus cycle is composed of at least two bus states and each bu s state requ ires one processo r clock period.
Additional bus states added to a single bus cycle are called wait states. See Bus Functional Description.
Since a bus cycle requires a minimum of two bus states (equal to two processor clock periods), data can be transferred between external devices and the Am386DXlDXL CPU at a maximum rate of one 4-byte Dword every two processor clock periods, for a maximum bus bandwidth of 80 Mb/s (Am386DXlDXL microprocessor operating at 40-MHz processor clock rate).
~1
BE1
150218-046 Figure 43. logic to Generate AO, A1 from BE3-BEO
74
Am386 Microprocessors for Personal ComputersA31
A31 A31 A31 A31 A31
FFFFFFFFH
OOOOOOOOH
Table 18. Generating A31-AO from BE3-BEO and A31-A2 Am386DX/DXL CPU Address Signals
...
A2 Physical BaseAddress ...
...
...
...
...
Physical Memory 4Gb
A2 A2 A2 A2 A2
A1 0 0 1 1
Physical Memory Space
BE3
AO
0
x
1 X
0 X
1 Low
SOOOOOFFH SOOOOOFSH (See note)
OOOOFFFFH
OOOOOOOOH
BE2
x
X Low High
64 Kb
1/0 Space BE1
X Low High High
BEO
Low High High High
Math Coprocessor (3S7DX)
Accessible Programmed 1/0 Space
Note: Since A31 is High during automatic communication with coprocessor, A31 High and MIlO Low can be used to easily generate a coprocessor select signal.
15021B-047 Figure 44. Physical Memory and 110 Spaces
Am386DXlDXL Microprocessor Data Sheet 75
~
AMDMemory and 1/0 Spaces
Bus cycles may access physical memory space or 1/0 space. Peripheral devices in the system may either be memory-mapped, or I/O-mapped, or both. As shown in Figure 44, physical memory addresses range from OOOOOOOOH to FFFFFFFFH (4 Gb) and 1/0 addresses from OOOOOOOOH to OOOOFFFFH (64 Kb) for pro-grammed 1/0. Note the 1/0 addresses used by the auto-matic 1/0 cycles for coprocessor communication are 800000F8H to 800000FFH, beyond the address range of programmed 1/0, to allow easy generation of a coprocessor chip select signal using the A31 and MOO signals.
Memory and 1/0 Organization
The Am3860XlOXL microprocessor datapath to mem-ory and 1/0 spaces can be 32- or 16-bits wide. When 32-bits wide, memory and 1/0 spaces are organized naturally as arrays of physical 32-bit Owords. Each memory or 1/0 Oword has four individually addressable bytes at consecutive byte addresses. The lowest-ad-dressed byte is associated with data signals 017-00;
the highest-addressed byte with 031-024.
The Am3860XlOXL microprocessor includes a bus control input, B816, that also allows direct connection to 16-bit memory or 1/0 spaces organized as a sequence of 16-bit word. Cycles to 32- and 16-bit memory or 1/0 devices may occur in any sequence, since the B816 control is sampled during each bus cycle. (See Oynamic Oata Bus Sizing.) The Byte Enable signals, BE3-BEO, allow byte granularity when addressing any memory or 1/0 structure, whether 32- or 16-bits wide.
Dynamic Data Bus Sizing
Oynamic Oata Bus Sizing is a feature allowing direct processor connection to 32- or 16-bit data buses for memory or 1/0. A single processor may connect to both size buses. Transfers to or from 32- or 16-bit ports are supported by dynamically determining the bus width during each bus cycle. Ouring each bus cycle an address decoding circuit or the slave device itself may assert B816 for 16-bit ports, or negate B816 for 32-bit ports.
With B816 asserted, the processor automatically converts operand transfers larger than 16 bits, or mis-aligned 16-bit transfers, into two or three transfers as required. All operand transfers physically occur on 015-00 when B816 is asserted. Therefore, 16-bit memories or 1/0 devices only connect on data signals 015-00. No extra transceivers are required.
Asserting B816 only affects the processor when BE2 andlor BE3 are asserted during the current cycle. If only 015-00 are involved with the transfer, asserting B816 has no affect since the transfer can proceed normally over a 16-bit bus whether B816 is asserted or not. In other words , asserting B816 has no effect when only the lower half of the bus is involved with the current cycle.
There are two types of situations where the processor is affected by asserting B816, depending on which Byte Enables are asserted during the current bus cycle.
Upper Half Only:
Only BE2 and/or BE3 asserted.
Upper and Lower Half:
At least BEl, BE2 asserted (and perhaps also BEO andlor BE3).
Effect of asserting B816 during Upper Half Only read cycles:
Asserting BS16 during Upper Half Only reads causes the Am3860XlOXL microprocessor to read data on the lower 16 bits of the data bus and ignore data on the upper 16 bits of the data bus. Oata that would have been read from 031-016 (as indicated by BE2 and BE3) will instead be read from 015-00, respectively.
Effect of asserting B816 during Upper Half Only write cycles:
Asserting BS16 during Upper Half Only writes does not af-fect the Am3860X/OXL microprocessor. When only BE2 and/or BE3 are asserted during a Write cycle, the Am3860XlOXL microprocessor always duplicates data signals 031-016 onto 015-00 (see Table 13). Therefore, no further Am3860X/OXL CPU action is required to per-form these writes on 32- or 16-bit buses.
Effect of asserting B816 during Upper anl=f Lower Half read cycles:
Asserting BS16 during Upper and Lower iHalf reads causes the processor to perform two 16-bit read cycles for complete physical operand transfer. Bytes 0 a~d 1 (as in-dicated by BEQ and BE1) are read on the first ewcle using 015-00. Bytes 2 and 3 (as indicated by BE2 an~ BE3) are read during the second cycle, again using \ 015-00.
031-016 are ignored during both 16-bit cycles.\BEQ and BEl are always negated during the second 16:!Jit cycle.
See Figure 54 Cycles 2 and 2a. . Effect of asserting B816 during Upper and Lower Half write cycles:
Asserting BS16 during Upper and Lower Half writes causes the Am3860XlOXL microprocessorto perform two 16-bit write cycles for complete physical operand transfer.
All bytes are available the first write cycle allowing external hardware to receive Bytes 0 and 1 (as indicated by BEQ and BEl) using 015-00. On the second cycle the Am3860XlOXL microprocessor duplicates Bytes 2 and 3 on 015-00 and Bytes 2 and 3 (as indicated by BE2 and B§) are written using 015-00. BEO and BEl are always negated during the second 16-bit cycle. BS16 must be as-serted during the second 16-bit cycle. See Figure 54 Cy-cles 1 and 1 a.
Interfacing with 32· and 16·Blt Memories
In 32-bit-wide physical memories such as Figure 45, each physical Dword begins at a byte address that is a multiple of 4. A31-A2 are directly used as a Dword selects and BE3-BEO as byte selects. B816 is negated for all bus cycles involving the 32-bit array.
76 Am3S6 Microprocessors for Personal Computers
When 16-bit-wide physical arrays are included in the system, as in Figure 46, each 16-bit physical word be-gins at an address that is a multiple of 2. Note the ad-dress is decoded to assert B8 16 only during bus cycles involving the 16-bit array. If desiring to use pipelined address with 16-bit memories, then BE3-BEQ and WfR are also decoded to determine when B816 should be asserted. (See Pipe lined Address with Dynamic Data Bus Sizing.)
A31-A2 are directly usable for addressing 32- and 16-bit devices. To address 16-bit devices, A1 and two Byte Enable signals are also needed.
To generate an A1 signal and two Byte Enable signals for 16-bit access, BE3-BEQ should be decoded as in Table 19. Note that certain combinations of BE3-BEQ are never generated by the Am386DXlDXL micropro-cessor, leading to "don't care" conditions inthe decoder.
Any BE3-BEQ decoder, such as shown in Figure 47, may use the non-occurring BE3-BEQ combinations to its best advantage.
32" Data Bus (D31-DO) Am386DX/DXL
Address Bus (BE3-BEO, A31-A2) 32-Bit
Microprocessor Memory
lBS16 High
Figure 45. Am386DXlDXL Microprocessor with 32·8it Memory 150218-048
Data Bus (D31-DO) 32/
Am386DXlDXL
""
32-BitMicroprocessor Address Bus Memory
\\
(BE3-BEo, A31-A2)BS16
I
Address DecoderI
16/ Data Bus (D15-DO)...
Address Bus (A31-A2) 16-Bit Memory (BE3-BEO) (BHE, BLE, A1)I
LogicI
150218-049 Figure 46. Am386DXlDXL Microprocessor with 32·811 and 16·811 Memory
Am386DXlDXL Microprocessor Data Sheet
n
I I
I I"
!
~
AMDTable 19. Generating Al, BHE, and BlE for Addressing 16-81t Devices
Am386DXlDXl CPU Signals 16-Blt Bus Signals
liD BE2 BEl BEO Al
-BLE asserted when 07-00 of 16-bit bus is active.
BHE asserted when 015-08 of 16-bit bus is active.
AlLow for all even words; A 1 High for all odd words.
X X X-non-contiguous bytes
L H
L L
L H
X X X-non-contiguous bytes
X X X-non-contiguous bytes
X X X-non-contiguous bytes
L L
X X X-non-contiguous bytes
L H
L L
* =A non-occurring pattern of Byte Enables; either none are asserted or the pattern has Byte Enables asserted for non-contiguous bytes.
Operand A"gnment
With the flexibility of memory addressing on the Am386DXlDXL microprocessor, it is possible to transfer a logical operand that spans more than one phy-sical Dword or Word of memory or I/O. Examples are 32-bit Dword operands beginning at addresses not evenly divisible by 4- or a 16-bit Word operand split between two physical Dwords of memory array.
Operand alignment and data bus size dictates when multiple bus cycles are required. Table 20 describes the transfer cycles generated for all combinations of logical operand lengths, alignment, and data bus sizing. When multiple bus cycles are required to transfer a multi-byte logical operand, the highest-order bytes are transferred first (but if B816 asserted requires two 16-bit cycles be performed, that part olthe transfer is lowest-order first).