ELEN0040 - Electronique num´erique

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ELEN0040 - Electronique num´ erique

Patricia ROUSSEAUX

Ann´ee acad´emique 2014-2015

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CHAPITRE 4

Sequential circuits

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1 Fundamentals of Sequential Circuits 1.1 Motivation

1.2 Synchronous and Asynchronous Circuits 1.3 State, State Diagram and State Table 1.4 Time simulation

2 Latches

3 Flip-Flops

4 State diagrams and State Tables

5 Finite State Machine Diagrams

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Real Basic Memory Element (1bit) : the LATCH (“Verrou”)

I state = 1 binary variable = 1 bit

I capability to force output to 0 or 1

I asynchronousstorage elements

I from basic to more elaborated latches : 1. basic (NOR)SRLatch

2. basic (NAND) ¯SR¯Latch 3. clockedSR Latches 4. D Latch

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Basic SR Latch

I Formed by 2 cross-coupled NOR gates

I Thestatesare defined by outputsQ, ¯Q which normally are reciprocally complemented values

I There are thus 2 useful states :

I theSet State:Q= 1, ¯Q= 0

I theReset State:Q= 0, ¯Q= 1

I There are two inputs :

I set inputS:S= 1brings the system in itsSet state

I reset inputR:R= 1brings the system in itsReset state

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SR Latch behavior

1. start withR= 0, S= 0, the stored state is initially unknown

2. S changes to 1, thissets Q to 1 3. S back to 0 ,Q “remembers” 1 thus, two input conditions cause the system to be in set state 4. R changes to 1, thisresetsQ to 0 5. Rback to 0, nowQ “remembers” 0

thus, two input conditions cause the system to be in reset state 6. suppose bothS andR changes to 1 7. bothQ and ¯Q are zero ! ! !,

undefined state

8. if bothR andS go to zero

Timing diagram

Race conditions :

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Timing diagram

Race conditions :

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Timing diagram

Race conditions :

In practice, it is very difficult to observe the SR Latch in the 1-1 state since one S or R usually changes first. The latch ambiguously returns to state 0-1 or 1-0.

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SR Latch state table

The time behavior of the SR Latch is summarized in the state table showing next state based on the current inputs (S,R) and the current stateQ(t)

S R Q(t) Q(t+ ∆)

0 0 0 0 hold previous state

0 0 1 1

0 1 0 0 reset

0 1 1 0

1 0 0 1 set

1 0 1 1

1 1 0 X forbidden

1 1 1 X

It can also be described by the following equation : Q(t+ ∆) =S+ ¯RQ(t)

∆ is the gate delay, the time between change in input and corresponding change in state. One usually writesQ(t+ 1).

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Basic ¯ S R ¯ Latch

The cross-coupling of 2 NAND gates presents a similar behavior with :

I S = 0 to switch to set state

I R= 0 to switch to reset state

I bothR= 0,S = 0 corresponds to an undefined state

S R Q(t) Q(t+ ∆)

1 1 0 0 hold previous state

1 1 1 1

1 0 0 0 reset

1 0 1 0

0 1 0 1 set

0 1 1 1

0 0 0 X forbidden

0 0 1 X

Q(t+ 1) = ¯S+RQ(t)

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Controlled SR Latch

I A control or “enable” or “clock” inputC is added

I The state can only change if the control input is high

I TheS,R inputs are only observed whenC is high

I The behavior and the state table are exactly the same as those of the SR Latch (with NOR gates) when C= 1

I When C= 0, the state remains unchanged, regardless of the values ofS andR

I The problem of the undefined state remains :C = 1,S = 1, R= 1

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D Latch

I The undefined state is removed by imposing necessarily different values to inputs S andR

I To this end, an inverter is added

I There remains one inputD :

I D= 1 is equivalent toS= 1

I D= 0 is equivalent toR= 1

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D latch : modes of operation

I When C= 0 : the latch is in itsmemorizing mode, the output is the memorized state

I When C= 1 : the latch is in itstransparent mode, the output follows the input

C D Q(t) Q(t+ 1)

0 X 0 0 memorizing mode

0 X 1 1

1 0 0 0 reset

1 0 1 0

1 1 0 1 set

1 1 1 1

Q(t+ 1) = ¯C Q(t) +CD

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2 Latches

3 Flip-Flops

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How to build a synchronous basic memory cell ?

I Using latches, the states can continuously change, following their input changes as long as the clock signal is high

I This undesired behavior for synchronous systems is linked to the feedback path from latches outputs to latches inputs through a combinational logic circuit

I This feedback path imposes the delay of the combinational logic circuit which computes latches inputs from present state

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The latch timing problem

I The simplest possible combinational circuit is an inverter

I The following simple circuit combines a D latch as memory cell and an inverter as combinational circuit

I Suppose initiallyY = 0

I As long asC = 1, the value ofY continues to change

I The changes are based on the delay present in the loop through the connection fromY toY

I Be careful

I the memory cell used is a stable circuit since it does not include an inverter in its internal feedback loop

I the problem comes from the external loop

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Solution : the Flip-Flop

I Thedesired behaviorfor synchronous clocked sequential circuits : the state can only changeonceper clock pulse

I The solution is to break the closed pathfrom the input to the output of the storage element

I Use Flip-Flop instead of latch

I Two types, depending on the triggering behavior

I Master-Slave Flip-¿Flop: the state change is triggered by thevalue (high or low) of the clock

I Edge-Triggered Flip-Flop: the state change is triggered by the positive (from 0 to 1) or negative (from 0 to 1) edgeof the clock

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S-R Master-Slave Flip-Flop

I is made of two clocked SR latches connected in cascade

I the clock is inverted for the second latch

I When C= 1 :

I The first latch=masterlatch is in itstransparentmode

I The input is observed from the first latch and passed to outputY

I The second latch=slavelatch is in itsmemorizingmode

I The past state is memorized, new stateY cannot pass toQ

I When C= 0 :

I The first latch is in itsmemorizingmode

I Any change in inputsS orR is not observed byY

I The second latch is in itstransparentmode

I Y memorized by the first latch is passed toQ

I In both cases,the path from inputsS andR to outputQ is broken

I As in SR latch,S =R= 1 is not allowed

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SR Flip-Flop : timing behavior

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The problem of “1s catching

I The inputs S and/or Rare allowed to change whileC = 1

I SupposeQ= 0, if

1. S goes to 1 then back to 0 and thenR goes to 1 and back to 0 whileC still at 1

I Y, output of the master latch, follows and goes to 1 and then to 0 afterR= 1

I finally 0 is passed to slave andQ= 0 2. S goes to 1 then back to 0 and thenR

remains 0

I Y is set to 1 and does not change anymore

I 1 is passed to slave andQ= 1

I The expected behavior is thatQ corresponds to the input values just before the clock goes to 0

I Case 1 is OK but unreliable

I Case 2 does not provide the expected output sinceQ was zero before the clock pulse andS andRare both zero just before the clock goes to 0

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Pulse-Triggered Flip-Flop vs. Edge-triggered Flip-Flop

I In SR Master-Slave flip-flop, any change inS,R duringC= 1 is taken into account : the 1s’ catching problem

I The new state is triggered by thevalueof the clock

I This behavior is sometimes difficult to master : if

I delays in combinational circuits are too high

I or unintentional changes occur

I Unexpected state changes can be observed

I Better use Edge-Triggeredflip-flops

I The state change is triggered by thetransitionof the clock

I positive edge-triggered flip-flop: whenC goes from 0 to 1 (rising edge)

I negative edge-triggered flip-flop: whenC goes from 1 to 0

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Negative Edge-Trigerred D Flip-Flop

The master clocked SR latch is replaced by a D latch

I When C= 1 :

I The input is observed from the first latch and passed to outputY as long asC is high

I The SR latch latch is in itsmemorizingmode

I The past state is memorized, new stateY cannot pass toQ

I When C= 0 :

I The SR latch is in itstransparentmode

I Y memorized by the D latch at the time instant just before clock transition from 1 to 0 is passed toQ

I The change of the D flip-flop output is associated with value of input Dat the negative edge of the pulse

I No 1s’ catching problem

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Positive Edge-Triggered D Flip-Flop

I An inverter is added to the clock input

I Q changes to the value ofD applied at the positive clock edge

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Standard symbols for storage elements

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JK Flip-Flop

I The behavior of the JK flip-flop is analogous to the SR master-slave flip-flop except thatJ =K = 1 is allowed

I For J=K = 1, the flip-flop changes to the complemented state

I As a master slave flip-flop it has the same 1s’ catching behavior as the SR flip-flop

I An edge-triggered JK flip-flop is preferred

I It uses an edge-triggered D flip-flop

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T Flip-Flop

I The behavior is the following

I forT = 0, no change in state

I forT = 1, change to the complemented state

I master-slave or edge-triggered

I the master-slave presents the 1s’ catching problem

I the edge-triggered is made from an edge-triggered D flip-flop

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Asynchronous direct inputs

I At power up or when needed, all or part of a sequential circuit has to be initialized to a known state before it begins operation

I This initialization is doneasynchronously, independently of the clocked behavior

I Direct Rand/or S inputs are used

I They control the state of the internal latches of the flip-flop

I For example :

I 0 applied toRinput resets the flip-flop to the 0 state

I 0 applied toSinput sets the flip-flop to the 1 state

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Summary

The following slides summarize the essential characteristics of the flip-flops, in terms of the :

I Characteristic table : this table defines the next state of the flip-flop in terms of the flip-flop inputs and current state

I Characteristic equation : the equation that defines the next state of the flip-flop as a Boolean function of the flip-flop inputs and current state

I Excitation table: this table defines the flip-flop input variables values needed to trigger a transition from the current state to the next state

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D Flip-Flop

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T Flip-Flop

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SR Flip-Flop

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JK Flip-Flop

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Flip-flop timing behavior : D, T

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Flip-flop timing behavior : SR, JK

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2 Latches

3 Flip-Flops

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Modeling of a sequential circuit

I The general model comprises a combinational circuit and a set of basic storage elements

I Synchronous systems :

I are driven by aclock

I useflip-flopsas storage elements

I all the flip-flops must share exactly the same clock signal

I all the flip-flops store their information at the same time

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Moore and Mealy models

I Sequential systems are also called Finite State Machines

I Two models depending on the way outputs are obtained : Moore Model

I The outputs are a functiononlyof states

ouput(t)=f(state(t))

Mealy Model

I The outputs are a function of statesandinputs

ouput(t)=f(state(t),inputs(t))

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State definition

I A state remember meaningful propertiesofpast input sequences that are essential to predictfuture output values

I Example : state A represents the fact that a sequence of two successive “1” has occurred as the most recent past two inputs

I Each of the states has be coded in binary values

I To representmstates, we need nbits with n≥ dlog₂me

I Each bit corresponds to a state variable

I Astate is defined by a combination of values of the state variables

I The state is linked to theflip-flopspresent in the circuit

I One flip flop contributes for one state variable

I Example : the design of a sequential system requires 4 states

I the representation of these 4 states requires 2 bits

I 2 flip-flops and 2 state variablesAandB

I Four states :

I S0 : 00

I S1 : 01

I S2 : 10

I S3 : 11

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State table and State diagram

The behavior of the system can be defined by :

I a logic diagram made of flip-flops and usual combinational gates

I the combinational part of the circuit is characterized theflip-flop input equations : the Boolean functions that define the inputs of the flip-flops

I a State Table: similar to the truth table for combinational circuits.

The state table presents

I the next state, i.e. the values ofstate variablesat timet+ 1

I the values of theoutputsat timet for all possibles combinations of values of :

I thepresentstate variables, at timetand

I theinputsat timet

I a State Diagram: a graphical form of the state table.

I Each state is represented by a circle, with the state name inside

I For each possible state transition, triggered by changes in the inputs, an arc is drawn from the present state to the next state

I Each arc is labeled with the inputs values that cause the state transition

I The corresponding outputs values are added to the labels or added to the state name (Moore model)

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Example 1 : Mealy model

I input:X(t)

I Output:Y(t)

I States: defined byA(t) andB(t), the two state variables

Four states :

I S0 : 00

I S1 : 01

I S2 : 10

I S3 : 11

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Example 1 : flip-flop input equations and output equation

I flip-flop input equations :

A(t+ 1) =A(t)X(t) +B(t)X(t) B(t+ 1) = ¯A(t)X(t)

I output equation :

Y(t) = ¯X(t)B(t)+ ¯X(t)A(t)

I the D flip-flops used indicate that input, output and state are defined at positive edge of the clock

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State table

or in more compact form

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State Diagram

I 4 states S0, S1, S2, S3

I one circle for each state

I 2 transitions from each state corresponding to X = 0 andX = 1

I The diagram, and thereof the problem, can be further simplified by mergingequivalent states

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Equivalent state definitions

I Two states areequivalentif their response for each possible input sequence is anidentical output sequence

I Or equivalently, two states are equivalentif their outputs produced foreach input valueis identicaland their next states foreach input valueare the same or equivalent

I States S2 and S3 are equivalent, same output and identical next state forX = 0 andX = 1

I S2 and S3 are merged in a new state S’2

I The new state S’2 and S1 are also equivalent

I They are merged into new state S’1

I Finally, 2 states remain which can be implemented using only one bit, and thus one state variable

I The system can be redesigned using only one flip-flop

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Example 1 : Moore and Mealy models

I The system combines Mealy and Moor models

I in state S0, the output does not depend on the input (always 0) : Moore model

I the output value is removed from the label on the arc and included in S0 circle

I for the other states, the output depends on the input : Mealy model

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Example 2 - Moore model

I The system is defined by its flip-flop input equation and its output equation

I inputs :X andY

I output :Z

I state variable :A

A(t+ 1) =A(t)⊕X(t)⊕Y(t) Z(t) =A(t)

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2 Latches

3 Flip-Flops

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R´ ef´ erences

I Logic and Computer Design Fundamentals, 4/E, M. Morris Mano Charles Kime , Course material

http ://writphotec.com/mano4/

I Cours d’électronique numérique, Aurélie Gensbittel, Bertrand Granado, Université Pierre et Marie Curie

http ://bertrand.granado.free.fr/Licence/ue201/

coursbeameranime.pdf

I Lecture notes, Course CSE370 - Introduction to Digital Design, Spring 2006, University of Washington,

https ://courses.cs.washington.edu/courses/cse370/06sp/pdfs/

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