ELEN0040 - Electronique num´erique

ELEN0040 - Electronique num´ erique

Patricia ROUSSEAUX

Ann´ee acad´emique 2014-2015

CHAPITRE 5

Sequential circuits design - Timing issues

Synchronization

I Synchronous systems may be subject to asynchronousinteractions :

I if connected to an asynchronous system

I or if connected to a synchronous system but with a different clock

I In both cases, the system if fed with asynchronous signals so that :

I changes in these asynchronous signals may arrive at inputs of flip-flops during the setup-hold time interval

I this implies that two flip-flops may respond differently, resulting in incorrect state

I Synchronizationof the inputs signals to the clock Y is needed

Example of incorrect behavior

I Consider the following circuit driven by the asynchronous input signal RDY

with One-Hot state assignment State State variables

y2 y1 y0

S0 0 0 1

S1 0 1 0

S2 1 0 0

Example : illustration of mis-functioning

I 1.

I Initial state : 001

I RDY changes to 1 in the setup time interval of the flip-flops

I flip-flopy0resets properly

I flip-flopy1fails to set

I y2remains unchanged

I incorrect state 000 results and remains

I 2.

I flip-flopy0fails to reset

I flip-flopy1sets properly

I y2remains unchanged

I sequence of incorrect states 011→110→ 101→011 ...

Introduction of a synchronizer

I The problem comes from the fact that RDY feedstwo different flip-flops (y0 andy1) whichreact in an opposite waywhen changes in RDY occur during their setup-hold time period

I A D flip-flop is placed in the path from RDY to the circuit so that changes in the output of this flip-flop do not occur during the setup-hold time period of flip-flops y₀,y₁

I The output of the synchronizer RDY S is synchronized with the clock

I A change in RDY S appears one flip-flop delay after the clock positive edge

Metastability

I What happens if RDY changes during the setup-hold time period of the synchronizing flip-flop ?

I In theory, 2 situations may arise :

1. the flip-flop correctly triggers and changes its output RDY S at the clock edge

2. the flip-flop does not trigger and RDY S will change one clock period later

Metastability (continued)

I Typical problem of bistable systems

I The metastable state is in between state 0 and state 1

I In case of flip-flop, when the input changes in a specific timing relation with the clock edge, the system is driven to the metastable state

I Output and input voltages are in between 0 and 1

I The system may remain in this state for an undetermined period of time

I It will eventually switch to the 0 or 1 state due to a small electronic noise

I The time before the system eventually settles at 0 or 1 can be longer that the clock period and lead tosystem failure

I Proposed solution : use a cascade of synchronizers to lower the probability of metastable behavior

CHAPITRE 6

Registers and Counters

1 Registers

1.1 Storage registers 1.2 Shift registers

1.3 General purpose register

2 Counters

2.1 Asynchronous counter 2.2 Synchronous counter 2.3 Serial and parallel counters

Register

Register

An-bitregisteris a set ofnbinary storage elements (usually flip-flops) More generally, a register is made of a set ofnflip-flops, possibly with additional combinational gates.

A register is used to :

I storea vector of binary values (binary word)

I perform shiftof binary words

I or other basic data processing tasks (see micro-operations) Two main types of registers :

I storageregisters

I shiftregisters

Storage or memory register

Synchronous system : all flip-flops are triggered by thesame clock Examplen= 2, state table

Present state Next state Output Q1(t) Q2(t) Q1(t+ 1)Q2(t+ 1) Q1(t) Q2(t)

for inputsE1E2=

00 01 10 11

0 0 00 01 10 11 0 0

0 1 00 01 10 11 0 1

1 0 00 01 10 11 1 0

1 1 00 01 10 11 1 1

Storage or memory register (continued)

I Expectation :

I a register can store information for multiple clock cycles

I a register can load anewinformation when required by the user

I Observed behavior

I each D flip-flop stores the information on its inputs for every clock cycle

I inputs change the value to be stored

I Use a signal to control when new values have to be stored. Two strategies

I use a signal to block the clock

I use a signal to control the feedback of the outputs of the register back to its inputs

Register with clock gating

I The signal connected to the clock input of each flip-flop is replaced by thegated clock signalGClock

I This later is obtained by OR’ing the clock signal and a Load Gclock =Load +Clock

I when Load = 1, the clock is passed through, and active on the C input of the flip-flops

I the new input values are loaded at each positive edge of the clock

I when Load = 0 , the clock signal is blocked

I the values are stored in the register

I Possible problem of clock skewlinked to the propagation delay introduced by the OR gate

Register with Load-controlled feedback

I A more reliable solution to selectively load a register

I Use D flip-flops with enable

I In each cell, a2-to-1 multiplexer is used to select between Load and Storage mode

I forLoad = 0, the values arestoredin the register

I forLoad = 1, inputs values areloadedin the register

I The clock signal is directly applied to the C input of all flip-flops

I More complex gating but free of timing problems

Serial Shift register

I Ashift registeris made of a chain of flip-flops

I It moves the data laterally within the register toward themostor the lesssignificant position

I For a move to the right, toward thelesssignificant bit, the flip-flops are interconnected as follows :

D_i =Q_i−1

I The data input E is called the serialinput

I The vector (Q₁,Q₂,· · · ,Q_n) is called theparallel output

I The data output Qnis theserial output

I At each clock pulse,

I the serial input E is placed at themostsignificant position

I bits 1 ton−1 are moved one position to theright

I the serial outputQn is removed from the register

Serial shift register (continued)

I The data can also be moved to the left, i.e. to themost significant bit position

Di =Qi+1

I The data output Q1is theserial output

I At each clock pulse,

I the serial input E is placed at thelesssignificant position

I bits 2 tonare moved one position to theleft

I the serial outputQ1is removed from the register

Shift register with parallel load

I A multiplexer is added before each flip-flop input to select between shiftandloadmode

I For right shift and the 2 most significant bits A and B :

I if SHIFT = 0, dataDA andDB are loaded and replace A and B, loadmode

I if SHIFT = 1, the previously loaded data are shifted one position to the right at each clock pulse, shiftmode

Shift register with parallel load and hold mode

I An additionalhold mode is obtained by adding a third AND gate

I Load and Shift are two control inputs

General register

I By placing a 4-input multiplexer in front of each D flip-flop, we can implement a circuit able to perform the 4 operations : parallel load, right shift, left shift and hold.

Registers : applications

I Temporary storage of information

I Parallel-serial conversion of binary words

I Serial-parallel conversion of binary words

I Combination of these last two applications is useful to interface digital systems distant from each other : one line instead ofn: the transmitter converts and send the data serially while the receiver accepts the data serially and converts back in parallel form

I Division by 2ⁿ =nright shifts

I Multiplication by 2ⁿ =nleft shits

1 Registers

1.1 Storage registers 1.2 Shift registers

1.3 General purpose register

2 Counters

2.1 Asynchronous counter 2.2 Synchronous counter 2.3 Serial and parallel counters

Counters

Counter

A counter is a sequential circuit that goes through a prescribed sequence of states upon the application of successive clock pulses

I A counter is made from a set of nflip-flops interconnected through combinational gates

I A binary counter follows the binary numbers sequence, from 0 to 2ⁿ−1

I Counters can also count down or count through other fixed sequence of numbers

Two main types of counters :

I asynchronousor ripplecounters : the flip-flop output transitions are used as the sources of triggering changes in other flip-flops,

asynchronous system

I synchronouscounters : all the flip-flops use a common clock signal, synchronous system

The simplest 1-bit counter

I This counter uses 1 flip-flop

I When there is a positive edge on the clock input, output A is complemented

I The counter goes through the sequence of states 0→1→0→1· · · : binary counter modulo-2

I This system is also called afrequency divider: the frequency of the output signal Q is equal to the frequency of the clock signal C divided by 2

Ripple counter

I A ripple counter is obtained by connectingncells of 1 bit counter

I The output of cell i is connected to the clock input of cell i+1

I The flip-flops are driven by different clock signals : asynchronous system

I With 2 bits :

I at a positive edge of the clock, A is complemented

I the clock input for flip-flop B is the output A

I when A changes from 0 to 1, this corresponds to a positive edge of clock input of B and B is complemented

Ripple counter (continued)

I The arrows show the cause-effect relationship, i.e.

the transitions that trigger a change in the next stage of the counter

I The changes “ripple” downward through the chain of flip-flops

I The counter goes through the sequence of states : 00→01→ 10→11→00→ · · ·

I For additional bits C,D,..., the frequency of the signal is divided by two at each stage

I For three bits, the bit C changes half as frequently as the bit B

I The sequence of states is :

000→001→010→011→100→101→110→111

Ripple counter - Fine timing

I Transition from state 011 to state 100 for counter modulo-8

I t_p is the propagation delay of each flip-flop

I The final delay is given by ntp I Asynchronous counters are slow

I We also observe transitorystates : before settling at the final state 100, due to the propagation delays, the system goes through the transitory states 010 and 000

Synchronous counters

I The “ripple” effects are eliminated by using :

I a common clock for all flip-flops

I a combinational circuit to generate the next state

I for an up-counter, use an incrementer

I for a down counter, use a decrementer

I for other functions, design the combinational circuit I Let us consider first an up-counter

I An incrementer can be easily derived from a ripple carry adder

I Consider a 4 bit incrementer : S=A+0001

I equations of the incrementer are :

S0= ¯A0 C1=A0

Si =Ai⊕Ci Ci+1=AiCi ,i = 1,2,3

I the first cell is a simple inverter

I the three other cells are half adders

I theSi variables are the inputs of the flip-flopsDi I theAi variables are the outputs of the flip-flopsQi

Synchronous counter modulo-4

I Count is enabled with input EN :

I EN=1, counter

I EN=0, storage register

Serial and parallel counter

I Serial counter

I the serial carry logic implies addition of the gate delays from stage 0 to stage 3

I Parallel counter

I a parallel gating logic can be derived from the carry lookahead adder

I there is only one gate delay

I this provides a faster counter

Counter with parallel load

I A general counter provides

I a parallel load capability for initializing the counter prior to the count operation

I a storage capacity to memorize the binary word for a given period

I two inputs Load and Count control the operation according to the function table

I n4-bit counters can be used to build a 4n-bit counter

I the Count signal is applied to the first stage

I the carry out CO of each stage is

Design example : synchronous BCD counter

Design a synchronous BCD counter using D flip-flops 1. number of flip-flops : 4

2. the state sequence to be implemented is

0000→0001→0010→0011→0100→0101→ 0110→0111→1000→1001→0000

3. derive the state table, states 1010 to 1111 are don’t care Present state Next state Q8 Q4 Q2 Q1 Q8 Q4 Q2 Q1

0 0 0 0 0 0 0 1

0 0 0 1 0 0 1 0

0 0 1 0 0 0 1 1

0 0 1 1 0 1 0 0

0 1 0 0 0 1 0 1

0 1 0 1 0 1 1 0

0 1 1 0 0 1 1 1

0 1 1 1 1 0 0 0

1 0 0 0 1 0 0 1

1 0 0 1 0 0 0 0

Synchronous BCD counter - equations

I Use K-maps to to optimize the flip-flop input equations Q8(t+ 1) =Q8Q¯1+Q1Q2Q4

Q₄(t+ 1) =Q₄⊕Q₁Q₂ Q2(t+ 1) =Q2Q¯1+ ¯Q8Q¯2Q1

Q1(t+ 1) = ¯Q1

I If the counter is perturbed and enters a unused state, the state transitions will be

Present state Next state Q8 Q4 Q2 Q1 Q8 Q4 Q2 Q1

1 0 1 0 1 0 1 1

1 0 1 1 0 1 0 0

1 1 0 0 1 1 0 1

1 1 0 1 0 1 0 0

1 1 1 0 1 1 1 1

1 1 1 1 1 0 0 0

I The system returns to a valid state in two clock cycles

I If this is not acceptable, a strategy has to be designed to detect such

Initialization

I The counter has to be initialized

I This has to be donesynchronously

I A general counter can be used, using the Load mode

I For incomplete state sequence (e.g. BCD counter), the system has to be initialized at a valid state

I Never use the asynchronous flip-flop inputs to initialize the counter in normal operation

I This should be done only at power-up or reset conditions

A very bad practice

I We want to build a modulo-7 counter

I We use a general 4-bit counter :

I detect the last state 0111

I and after detection use the clear input of the counter to go back to state 0000

I But, the clear input acts directly on the asynchronous reset inputs of the flip-flops

I and the transition to 0000 willnot happen at a clock edge

I Existence of state 7 may not be long enough to reliably reset all flip-flops to 0. Referred to as a “suicide” counter !

A better solution

I Detect state “6” : 0110 withQ2Q1 I This set load to 1

I The 0000 present on the inputsD3to D₁are loaded

I The counter switches synchronously to state 0000 as required

R´ ef´ erences

I Logic and Computer Design Fundamentals, 4/E, M. Morris Mano Charles Kime , Course material

http ://writphotec.com/mano4/

I Cours d’´electronique num´erique, Aur´elie Gensbittel, Bertrand Granado, Universit´e Pierre et Marie Curie

http ://bertrand.granado.free.fr/Licence/ue201/

coursbeameranime.pdf

I Lecture notes, Course CSE370 - Introduction to Digital Design, Spring 2006, University of Washington,

https ://courses.cs.washington.edu/courses/cse370/06sp/pdfs/