ELEN0040 - Electronique num´erique

ELEN0040 - Electronique num´ erique

Patricia ROUSSEAUX

Ann´ee acad´emique 2014-2015

CHAPITRE 6

Registers and Counters

Design of a modulo-8 binary counter using JK Flip-flops

I 3 bits are required = 3 flip-flops

I State table

Present State Next State Flip-flop inputs

Q2 Q1 Q0 Q2 Q1 Q0 J2 K2 J1 K1 J0 K0

0 0 0 0 0 1 0 X 0 X 1 X

0 0 1 0 1 0 0 X 1 X X 1

0 1 0 0 1 1 0 X X 0 1 X

0 1 1 1 0 0 1 X X 1 X 1

1 0 0 1 0 1 X 0 0 X 1 X

1 0 1 1 1 0 X 0 1 X X 1

1 1 0 1 1 1 X 0 X 0 1 X

1 1 1 0 0 0 X 1 X 1 X 1

I Flip-flop inputs are derived from the excitation table Q(t) Q(t+ 1) J K

0 0 0 X

0 1 1 X

1 0 X 1

1 1 X 0

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Flip-flop input equations

J2=Q1Q0

J1=Q0

J₀= 1

Ki =Ji, i= 0,1,2

Initialization

I The counter has to be initialized

I This has to be donesynchronously

I A general counter can be used, using the Load mode

I For incomplete state sequence (e.g. BCD counter), the system has to be initialized at a valid state

I Never use the asynchronous flip-flop inputs to initialize the counter in normal operation

I This should be done only at power-up or reset conditions

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A very bad practice

I We want to build a modulo-7 counter

I We use a general 4-bit counter :

I detect state “7” : 0111

I and after detection use the clear input of the counter to go back to state 0000

I But, the clear input acts directly on the asynchronous reset inputs of the flip-flops

I state “7” is transitory

I and the transition to 0000 willnot happen at a clock edge

I Existence of state 7 may not be long enough to reliably reset all flip-flops to 0. Referred to as a “suicide” counter !

A better solution

I Detect state “6” : 0110 withQ2Q1 I This set load to 1

I The 0000 present on the inputsD3to D₁are loaded

I The counter switches synchronously to state 0000 as required

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1 Registers

1.1 Storage registers 1.2 Shift registers

1.3 General purpose register

2 Counters

2.1 Asynchronous counter 2.2 Synchronous counter 2.3 Serial and parallel counters

3 Register transfers

3.1 Datapath, control unit and microoperations 3.2 Register transfer operations and RTL language 3.3 Microoperations

3.4 Register transfers design 3.5 Bus-based transfers 3.6 Serial operations

Datapath, control unit and microoperations

I The information stored in a digital system can be classified as data or controlinformation

I The system is accordingly split into two parts :

I thedatapathwhich performs data processing operations

I thecontrol unitwhich determines the sequence of operations

I Thedatapathis defined by its registers and the operations performed on the data stored in the registers

I An elementary operation is called a microoperation: e.g. loading of data into one register, transferring data between two registers, adding the contents of two registers,...

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Datapath and control unit communication

I Control andstatussignals allow the communication between the two parts :

I the control unit feeds the datapath with the control signals that characterize the operation to be performed

I the control unit receivesstatus signalsfrom the datapath

I the status signals inform the control unit about the state of the datapath

I this information is used by the control unit to determine the values of the control signals

I Additional signals, control inputs and control outputs, interact with other parts of the whole system

I Data can also be interchanged through data inputs and data outputs

Microoperations

I Amicrooperationis an elementary operation actingidentically onall bits of the register and lasting a clock cycle at most.

I Microoperations can be classified into 4 categories :

I transfer : copy the data from one register to another

I arithmetic : perform arithmetic operation on data in registers (+,-,1’s complement,...)

I logic : manipulate data or use bitwise operation (and,or, ...)

I shift : shift data in registers

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Transfer operation and Register Transfer Language (RTL)

I Manipulation of registers use a particular notation denoted by Register Transfer Language

I letters and numbers denote a register : R2, PC, ...

I parentheses are used to limit a range of register bits : R1(3), R2(1 : 4), PC(L)

I Adata transferis denoted by an arrow : R2←R1 :

I the contents of R1 is copied into R2

I the contents of R1 is unchanged

I the transfer should be done in one clock cycle (microoperation)

I A transfer assumes that datapath circuits from outputs to inputs of registers are available (see bus)

Conditional transfer

I Aconditional transfer occurs when a given condition is satisfied if (K₁= 1) then (R2←R1)

This is denoted by :

K₁: (R2←R1)

I K₁is a control variable which acts on the load input of the register

I signal K1has to be synchronized to the clock

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Arithmetic microoperations

RTL microoperation Description R0←R1 +R2 addition

R0←R1 1’s complement

R0←R1 + 1 2’s complement

R0←R2 +R1 + 1 subtraction (2’s compl.) R0←R1 + 1 increment

R0←R1−1 decrement Example :

X K¯ ₁: R1←R1 +R2 XK1: R1←R1 +R2 + 1

I in the transfer operation, R1←R1 +R2, ‘+’ means arithmetic addition

I the variable K1enables the operation

I when K1= 1 the result is placed in R1 and replace the previous contents

I when K₁= 0 no operation occurs, the contents of R1 is unchanged

I the variable X selects between addition and subtraction

Logical microoperations

RTL microoperation Description

R0←R1 bitwise NOT

R0←R1∨R2 bitwise OR (set bits) R0←R1∧R2 bitwise AND (clear bits) R0←R1⊕R2 bitwise XOR (complement bits) Example :

(K₁+K₂) : R1←R1∨R3

I in the expressionK1+K2, ‘+’ means logical OR

I in the transfer operation R1←R1∨R3, ‘∨’ means bitwise logical OR

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Logical microoperations (continued)

LetR1 = 10101010

I The OR microoperation can be used to set bits to 1 in the destination register when an appropriatemaskis applied : for example, set 4 most significant bits to 1

1010 1010 R1 (data)

1111 0000 R2 (mask)

1111 1010 R1←R1∨R2

I The AND microoperation is used to reset bits to 0 :

1010 1010 R1 (data)

0000 1111 R2 (mask)

0000 1010 R1←R1∧R2

I the XOR microoperation can be used to complement bits :

1010 1010 R1 (data)

1111 0000 R2 (mask)

0101 1010 R1←R1⊕R2

Shift microoperations

I Registers can be shifted to the leftor to theright, let R2 = 11001001

I leftshift :

R1←slR2 R1 = 10010010 a zero is entered at the least significant bit

I rightshift :

R1←srR2 R1 =01100100 a zero is entered at the most significant bit

I sometimes, a separate flip-flop is used to provide the data shifted in or to memorize the data shifted out

I other shifts may be considered (rotate bits, ...)

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Microoperations on a single register

I Using control signals, several microoperations can be associated to a register. Examples :

1. general register with shift, parallel load and hold modes 2. K1: R0←R1, K¯1K2: R0←R2

3. CX : A∨B, CY : A⊕B

I These operations correspond to register transfers

I The source register or/and the microoperation has to be selected through a combinational circuit

I As already seen for example 1, the selection can be made using a multiplexer

I An alternative approach consists in designing then-bit register with its combinational logic as the association of nidentical register cells.

A conventional approach is used for the design of the register cell

I If the same logic is used for each operation and/or source = dedicated logic

I If the combinational circuit can be shared by several sources or microoperations :shared logic

I The case of possible multiple destination registers will be considered later

Register transfers : selection through a multiplexer

I Consider example 2, where the source register has to be selected according to control variables K1,K2

I An-bit 2-to-1 multiplexer is used

I The selection inputS is simply given byK1 I When :

I K1= 1, the value in registerR1 is transferred into registerR0

I K1= 0 andK2= 1, the value in registerR2 is transferred into registerR0

I in both cases, the Load input of the register is high and transfer is activated

I otherwise (K1= 0, K2= 0) :

I the Load input of the register is low

I the previous value in registerR0 remains unchanged (hold mode)

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Register transfers : Selection through a multiplexer

I The procedure can be generalized to nsources : outputs of dedicated logic blocks, registers or shared logic blocks

I the control signals areK0,· · · ,Kn−1

I only one control signal is equal to one at any time

I the control signals are encoded to provide the selection inputs of the multiplexer

Register transfers design

I Specifications: one has to define for example 3

I the destination register

I the data inputs to the register

I the control inputs and their useful combinations

I the set of register functions, i.e. the register transfers

I the hold mode : hold the current register state

A B

(CX,CY), with combinations (0,0),(0,1),(1,0)

CX : A∨B , (1,0) CY : A⊕B, (0,1) (0,0)

I Design procedure:

I using a multiplexer

I using an individual cell design

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Example 3, selection through a multiplexer

I The register transfers to be implemented are : CX : A∨B, CY : A⊕B

I when CX= 0,CY = 0 : hold mode

I an encoder is not required, CX,CY are directly applied to the selecting inputs of the multiplexer

Example 3, selection through a multiplexer (continued)

I Consider the circuit cell for one bit of the register

I the decoder can be shared by all cells

I gate input cost :

I decoder : 8

I non-shared logic : 2+8+9=19, for each bit

I for the whole circuit : 8 + 19n+ 2 (shared logic, non-shared logic, one 2-OR gate)

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Example 3, individual cell design

Use the procedure defined in Chapter 5 for celli

I State table

Present state Next state

Ai(t) Ai(t+ 1) forCX CY Bi(t) =

000 001 010 011 100 101

0 0 0 0 1 0 1

1 1 1 1 0 1 1

I flip-flop input equation :

Ai(t+ 1) =CX Bi+ ¯Ai(CY Bi) +AiCY+AiB¯i

=CX Bi+ ¯Ai(CY Bi) +Ai(CY+ ¯Bi)

=CX Bi+ ¯Ai(CY.Bi) +AiCY.Bi

=CX Bi+Ai⊕CY Bi I gate input cost :

I for one cell : 2 (CX.Bi) + 2 (CY.Bi) + 8(XOR) + 2(OR) = 14

I for the whole circuit = 14n!

Register transfers with multiple destination registers

I Digital systems have many registers

I Paths must be provided to transfer data from one register to the other

I A particular destination register has to be selected for each microoperation

I A possible solution is to use a multiplexer dedicated to each destination register

I Better solution : use a bus, i.e. a communication path shared by all register, and a single multiplexer to select the source

I Buses can be implemented using :

I multiplexers

I three state buffers

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Dedicated MUX-Based transfers

A very flexible transfer structure

I selection signalsSi select the source register(s)

I control signalsLi select the destination register(s)

Possible transfers

Select Load

Register transfer S₂ S₁ S₀ L₂ L₁ L₀

R0←R2 1 0 0 0 0 1

R0←R1,R2←R1 0 1 0 1 0 1

R0←R1,R1←R0 0 1 1 0 1 1

...

Multiplexer Bus

I The multiplexer selects the source register

I The control signalsL_i select the destination register(s)

I Possible transfers

Select Load

Register transfer S₁ S₀ L₂ L₁ L₀

R0←R2 1 0 0 0 1

R0←R1,R2←R1 0 1 1 0 1

R0←R1,R1←R0 impossible ...

I A single bus driven by a multiplexer lowers the cost (less

communication links, a single multiplexer) but limits the available transfers

I Simultaneous transfers with different sources in a single clock cycle are impossible

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Buffer and Three-state buffer

I Abuffer:

I simply copies the input variable :F =X

I is used to improve circuit voltage levels and increase the speed

I Athree-state buffer

I presents a high-impedance output, giving three states : 0, 1 and High-Z

I the High-Z value behaves as anopen circuit

I X is the data input andE is a control input

I Outputs of several 3-state buffers can be connected together provided that all outputs but one are in High-Z state

Selection circuit using 3-state logic

I Performing data selection with 3-state buffers

I 2 buffer outputs are connected together

I Data Selection Function : if S = 0, OL = IN0, else OL = IN1

I Since EN0 = S and EN1 =S, one of the two buffer outputs is always High-Z

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Three-state bus

I The multiplexer is replaced by 3-state buffers

I A three-state buffer is connected at the output of each flip-flop composing the register

I The enable signalEN is identical for all bits

I The inputs of the flip-flops are connected to the bus, most generally through a buffer (not represented in the figure)

I This provides a bi-directional bus

I The transfer capabilities are identical to those of the multiplexer-bus

3-state register with bidirectional lines

3-state bus

Serial transfers

I A system operates in serial mode if the information is transferred or manipulated (microoperation) one bit at a time

I The bits are shifted out of one register and into a second register

I This is done with shift registers, the serial output of the first register is connected to the serial input of the second register

I Example : the transfer of one binary word of 4 bits takes 4 clock cycles

I The operation is controlled by the clock-gated Shift variable

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Serial microoperation example : 4bit-addition

I Two shift registers with parallel load capability are used for operands of the operation : A, B

I The two operands are loaded in parallel in the registers

I The operands are shifted at each clock cycle

I A full adder is used to compute the sum

I One additional flip-flop is used to store the carry

I Register A is also used to store the final result which is entered serially

I The final carry is stored in the flip-flop

R´ ef´ erences

I Logic and Computer Design Fundamentals, 4/E, M. Morris Mano Charles Kime , Course material

http ://writphotec.com/mano4/

I Cours d’´electronique num´erique, Aur´elie Gensbittel, Bertrand Granado, Universit´e Pierre et Marie Curie

http ://bertrand.granado.free.fr/Licence/ue201/

coursbeameranime.pdf

I Lecture notes, Course CSE370 - Introduction to Digital Design, Spring 2006, University of Washington,

https ://courses.cs.washington.edu/courses/cse370/06sp/pdfs/

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