Radiation Hardness Comparison of CMOS Image Sensor Technologies at High Total Ionizing Dose Levels

(1)

an author's https://oatao.univ-toulouse.fr/23035

Rizzolo, Serena and Goiffon, Vincent and Corbière, Franck ,... [et al.] Radiation Hardness Comparison of CMOS Image Sensor Technologies at High Total Ionizing Dose Levels. (2018) In: Radiation Effects on Optoelectronic Detectors (CNES Workshop), 28 November 2018 (Toulouse, France). (Unpublished)

(2)

S. Rizzolo, V. Goiffon, F. Corbière, R. Molina, A. Chabane,

S. Girard, P. Paillet, P. Magnan, A. Boukenter, T. Allanche,

C. Muller, C. Monsanglant Louvet, M. Osmond,

H. Desjonqueres, J-R Macé, P. Burnichon, J-P Baudu,

S. Plumeri

Radiation Hardness

Comparison of CMOS Image

Sensor Technologies at High

Total Ionizing Dose Levels

(3)

Context and motivation

CAMRAD project looks to develop and test under

real

conditions

a high-performance imaging system:



Characterization and monitoring of

nuclear wastes



Maintenance and instrumentation of

nuclear facilities

Characteristics of the prototype:



CMOS based color camera



High resolution



Compact design

(4)

CAMRAD project looks to develop and test under

real

conditions

a high-performance imaging system:



Characterization and monitoring of

nuclear wastes



Maintenance and instrumentation of

nuclear facilities

Characteristics of the prototype:



CMOS based color camera



High resolution



Compact design



Radiation hardness at TID > 1 MGy(SiO

₂

)

Context and motivation

Exploration study on lab test chips to identify the

best candidate for the final prototype

(5)

CAMRAD investigated CMOS Image Sensors



TID up to 1MGy(SiO

₂

)



4 CMOS Image Sensors

designed at ISAE-SUPAERO



3 180 nm CIS processes



2 readout chain architectures



Mixed 3.3 V and 1.8 V MOSFETs



Full 1.8 V MOSFETs



16 pixel designs



Standard 3T photodiode



Partially Pinned 3T photodiode



Radiation hardened by design

(6)

Overview on the standard CIS photodiodes

P- _substrate STI

P

N+

N CIS

RST PMD

SCR

STI STI

P

N+

N CIS

RST P + P+ _STI STI PMD

SCR

Pinned Photodiode

P

N+

N CIS

RST STI PMD

SCR

TG

N CIS

P+

Partially Pinned Photodiode

Standard 3T Photodiode

Pinning Layer (P

+

_doped)



Widely evaluated under

irradiation.



STI positive trapped

charges lead to a short

circuits between pixels



Change of the

photodiode

capacitance



Never investigated

under irradiation



P+ implant to cover the

N region



Prevent the contact

between the depletion

region and the oxides



PPD suffers from severe

degradation due to TID

o

Charge transfer

degradation

o

dark current

increase



Trapped charges in the

PMD and in the spacers.

B. Pain et al. , Proc. SPIE, vol. 5167, 2004

B. R. Hancock et al., Proc. SPIE, vol. 4306, 2001

P. R. Rao et al., Solid-State Electron, vol. 52, 2008.

V. Goiffon et al., IEEE Trans. Nucl. Sci., vol. 61, 2014

(7)

Overview on the standard CIS photodiodes

P

N+

N CIS

RST PMD

SCR

STI STI

P

N+

N CIS

SCR

Pinned Photodiode

P

N+

N CIS

RST STI PMD

SCR

TG

N CIS

P+

Partially Pinned Photodiode

Standard 3T Photodiode

Pinning Layer (P

+

_doped)



Widely evaluated under

irradiation.



STI positive trapped

charges lead to a short

circuits between pixels



Change of the

photodiode

capacitance



Never investigated

under irradiation



P+ implant to cover the

N region



Prevent the contact

between the depletion

region and the oxides



PPD suffers from severe

degradation due to TID

o

Charge transfer

degradation

o

dark current

increase



Trapped charges in the

PMD and in the spacers.

B. Pain et al. , Proc. SPIE, vol. 5167, 2004

B. R. Hancock et al., Proc. SPIE, vol. 4306, 2001

P. R. Rao et al., Solid-State Electron, vol. 52, 2008.

V. Goiffon et al., IEEE Trans. Nucl. Sci., vol. 61, 2014

(8)

P

N+

N CIS

RST PMD

SCR

STI STI

P

N+

N CIS

SCR

Partially Pinned Photodiode

Standard 3T Photodiode

Gate Overlap pixel design

P- _substrate

P

N+

N CIS

RST

P

d

SCR

1. Study the influence of the manufacturing process on the

CIS radiation hardness

2. Investigate the radiation effects in different photodiodes

design and radiation hardened by design solutions

CAMRAD Project:

Studied photodiode structures

(9)

CAMRAD investigated CMOS Image Sensors



TID up to 1MGy(SiO

₂

)



4 CMOS Image Sensors



3 180 nm CIS processes



2 readout chain architectures



Mixed 3.3 V and 1.8 V MOSFETs



Full 1.8 V MOSFETs

1. Study the influence of the manufacturing process on the

CIS radiation hardness

(10)

Readout chain degradation at TID up to 100 Mrad

[5] V. Goiffon, IEEE NSREC 2017, New Orleans, LA

0

0.2

0.4

0.6

0.8 0.0001 0.001 0.01

0.1

1 M

OSFET

V

th

Shift

(

V

)

Dose (MGy(SiO

₂

))

Pre Rad

Foundry C [5]

Foundry A

Foundry B



Manufacturing process impacts

the radiation hardness of the

readout chain:



TID MOSFETs V

_th

shift depends

on the technology

(11)

0

0.2

0.4

0.6

0.8 0.0001 0.001 0.01

0.1

1 M

OSFET

V

th

Shift

(

V

)

Dose (MGy(SiO

₂

))

Pre Rad

P MOSFETs

Readout chain degradation at TID up to 100 Mrad

3.3 V

MOSFETs

1.8 V

MOSFETs



Manufacturing process impacts

the radiation hardness of the

readout chain:



TID MOSFETs V

_th

shift depends

on the technology



1.8 V MOSFETs exhibit the lower

(12)

0

0.2

0.4

0.6

0.8 0.0001 0.001 0.01

0.1

1 M

OSFET

V

th

Shift

(

V

)

Dose (MGy(SiO

₂

))

Pre Rad

3.3V MOSFETs

Readout chain degradation at TID up to 100 Mrad



Manufacturing process impacts

the radiation hardness of the

readout chain:



TID MOSFETs V

_th

shift depends

on the technology



1.8 V MOSFETs exhibit the lower

threshold voltage shift



N MOSFETs threshold voltage

induced shift is less than in P

MOSFETs

(13)

TID induced dark current increase

P- _substrate N+

N CIS

RST

d

SCR

P

Gate Overlap pixel design

1.8V CIS Foundry C [5]

1.8V CIS Foundry A

1.8V CIS Foundry B

1.E-04

1.E-03

1.E-02

1.E-01

1.E+00

0.00010.001 0.01 0.1

1 D

a

rk

C

urrent

(

pA)

Dose (MGy(SiO

₂

))

3.3V CIS Foundry C [5]

3.3V CIS Foundry A

3.3V CIS Foundry B

Pre Rad

(14)

TID induced dark current increase

1. Manufacturing process impacts dark current CIS performances

before and

after TID up to 100 Mrad

 CISs from

foundry B

have the highest dark

current

2. 1.8 V CISs exhibit the best dark current values

after irradiation



7X reduction @100 Mrad for foundry C

N CIS

RST

d

SCR

P

Gate Overlap pixel design

1.8V CIS Foundry C [5]

1.8V CIS Foundry A

1.8V CIS Foundry B

1.E-04

1.E-03

1.E-02

1.E-01

1.E+00

0.00010.001 0.01 0.1

1 D

a

rk

C

urrent

(

pA)

Dose (MGy(SiO

₂

))

3.3V CIS Foundry C [5]

3.3V CIS Foundry A

3.3V CIS Foundry B

Pre Rad

(15)



Manufacturing process impacts the two main

radiation induced degradations:



Readout chain

MOSFETs threshold voltage shift

is minimized

in

Foundry B

CISs



Lower dark current

values are exhibited by

Foundry A

CISs



Non-uniformity appears in the pixel array for Foundry B CISs



For all the tested technologies:



1.8V MOSFETs

exhibit the lower threshold voltage shift



N MOSFETs

are the most radiation tolerant.



1.8V sensors

exhibit the best dark current performances

Sum up 1/2:

Manufacturing process impact

Sensor B 3.3 V

after 1 MGy(SiO

₂

)

Dark current reduction:

5X

Foundry A

4X

Foundry B

7X

Foundry C

(16)

CAMRAD investigated CMOS Image Sensors



TID up to 1MGy(SiO

₂

)



16 pixel designs



Standard 3T photodiode



Partially Pinned 3T photodiode



Radiation hardened by design

photodiodes

2. Improve TID degradation

understanding in different photodiodes design

P-_substrate STI P N+

N CIS

RST P d SCR P-_substrate STI P N+

N CIS

RST PMD SCR STI STI P P-_substrate STI P P N+

N CIS

RST P+ _P+ _STI STI PMD SCR

(17)

Dark current evolution with TID:

Radiation hardness of partially pinned photodiode

Standard 3T

Photodiode

P- _substrate STI N+

N CIS

RST PMD

SCR

STI STI

P

Partially Pinned

Photodiode

P

N+

N CIS

RST P+ STI STI PMD

SCR

1.E-16

1.E-15

1.E-14

1.E-13

1.E-12

1.E-11

0.001

0.01

0.1

1 D

a

rk

C

urrent

(

A)

Dose (MGy(SiO

₂

))

Pre Rad

(18)

Standard 3T

Photodiode

N CIS

RST PMD

SCR

STI STI

P

1.E-16

1.E-15

1.E-14

1.E-13

1.E-12

1.E-11

0.001

0.01

0.1

1 D

a

rk

C

urrent

(

A)

Dose (MGy(SiO

₂

))

Dark current evolution with TID:

Radiation hardness of partially pinned photodiode

3X

Trapped

charges and

interface

states in PMD

and STI

Trapped charges in the PMD

↓

P+ effective doping reduction

Partially Pinned

Photodiode

P

N+

N CIS

RST P+ STI STI PMD

SCR

Partially pinned

photodiode fails after

1 Mrad (SiO

₂

)!!

(19)

Standard 3T

Photodiode

N CIS

RST PMD

SCR

STI STI

P

1.E-16

1.E-15

1.E-14

1.E-13

1.E-12

1.E-11

0.001

0.01

0.1

1 D

a

rk

C

urrent

(

A)

Dose (MGy(SiO

₂

))

Dark current evolution with TID:

Radiation hardness of partially pinned photodiode

3X

15X

Trapped

charges and

interface

states in PMD

and STI

N CIS

RST

d

SCR

P

Gate overlap

design

Polysilicon

gate shields

the junction

from positive

charges

Partially pinned

photodiode fails after

1 Mrad (SiO

₂

)!!

Partially Pinned

Photodiode

P

N+

N CIS

RST P+ STI STI PMD

SCR

Trapped charges in the PMD

↓

P+ effective doping reduction

(20)

N CIS

RST

d

SCR

P

Gate overlap

design

Dark current VS Gate voltage:

The influence of the gate overlap

0 1E-12

2E-12

3E-12

-1.5 -1 -0.5 0 0.5

1

1.5 D

a

rk

C

urrent

(

A)

Gate Voltage (V)

d = 0.3 µm

d = 0 µm

d = 0.6 µm

10 Mrad, @22°C

(21)

Dark current VS Gate voltage:

The influence of the gate overlap

Enhanced Gate

Induced Drain

Leakage (GIDL) in

the gate overlap

structures

Negative

Gate Voltages

0 1E-12

2E-12

3E-12

-1.5 -1 -0.5 0 0.5

1

1.5 D

a

rk

C

urrent

(

A)

Gate Voltage (V)

d = 0.3 µm

d = 0 µm

d = 0.6 µm

N CIS

RST

d

SCR

P

Gate overlap

design

10 Mrad, @22°C

(22)

RST N+

P

STI

N+

SCR

N CIS

P- _substrate

d = 0µm

0 1E-12

2E-12

3E-12

-1.5 -1 -0.5 0 0.5

1

1.5 D

a

rk

C

urrent

(

A)

Gate Voltage (V)

d = 0.3 µm

d = 0 µm

d = 0.6 µm

Dark current VS Gate voltage:

The influence of the gate overlap

Induced defects in

the spacer

contribute to the

dark current

Positive Gate Voltages

Negative

Gate Voltages

Enhanced Gate

Induced Drain

Leakage (GIDL) in

the gate overlap

structures

N CIS

RST

d

SCR

P

Gate overlap

design

10 Mrad, @22°C

(23)

RST N+ N+

SCR

STI

N CIS

P

P- _substrate

P

d > 0 µm

Dark current VS Gate voltage:

The influence of the gate overlap

The overlap between the gate and the photodiode

protect from TID induced defects in the spacer

Best dark current for Gate Voltage > 0 V



Charge drain mechanism?

RST N+

P

STI

N+

SCR

N CIS

P- _substrate

d = 0µm

0 1E-12

2E-12

3E-12

-1.5 -1 -0.5 0 0.5

1

1.5 D

a

rk

C

urrent

(

A)

Gate Voltage (V)

d = 0.3 µm

d = 0 µm

d = 0.6 µm

Induced defects in

_{the spacer}

contribute to the

dark current

Positive Gate Voltages

Negative

Gate Voltages

Enhanced Gate

Induced Drain

Leakage (GIDL) in

the gate overlap

structures

(24)

N CIS

N

+

N CIS

N

+

Gate Overlap

Gate Overlap and N

+

_Drain

Investigation on the charge drain mechanism:

The proposed drain design

N

+

_{ring biased at VDD}

N CIS

RST N+ N+

N CIS

P

N+

d

STI

RST N+ N+

STI

N CIS

P

d

(25)

Investigation on the charge drain mechanism:

Dark current VS TID

1.E-16

1.E-15

1.E-14

1.E-13

1.E-12

1.E-11

0.001

0.01

0.1

1 D

a

rk

C

urrent

(

A)

Dose (MGy(SiO

₂

))

Gate Overlap and N+_Drain Gate Overlap

Pre Rad

N CIS

N

+

N CIS

N

+

Gate Overlap

Gate Overlap and N

+

_Drain

N

+

_{ring biased at VDD}

N CIS

RST N+ N+

N CIS

P

N+

d

STI

RST N+ N+

STI

N CIS

P

d

(26)

Investigation on the charge drain mechanism:

Dark current VS Gate voltage at moderate TID

1.E-16

1.E-15

1.E-14

1.E-13

1.E-12

1.E-11

0.001

0.01

0.1

1 Da

rk

Cu

rre

nt

(

A)

Dose (MGy(SiO

₂

))

Pre Rad

1E-14

1E-13

1E-12

1E-11

-1.5 -1 -0.5 0 0.5 1 1.5 2

D

a

rk

C

urrent

(

A)

Gate Voltage (V)

10 kGy, @22°C



At TID < 10 Mrad

dark current decrease

with the increase of gate

(27)

N CIS

RST N+ N+

SCR

N CIS

P

N+

d

STI

Investigation on the charge drain mechanism:

Dark current VS Gate voltage at moderate TID

RST N+ N+

SCR

STI

N CIS

P

P- _substrate

P

d

Gate Overlap

and N

+

_Drain



At TID < 10 Mrad

dark current decrease

with the increase of gate

voltage is observed in N

+

_{Drain design pixels}



The charge drain mechanism is confirmed thanks to

VDD N

+

_drain

1.E-16

1.E-15

1.E-14

1.E-13

1.E-12

1.E-11

0.001

0.01

0.1

1 Da

rk

Cu

rre

nt

(

A)

Dose (MGy(SiO

₂

))

Pre Rad

1E-14

1E-13

1E-12

1E-11

-1.5 -1 -0.5 0 0.5 1 1.5 2

D

a

rk

C

urrent

(

A)

Gate Voltage (V)

10 kGy, @22°C

(28)



At TID > 10 Mrad

dark current decreases

with the increase of

gate voltage in both pixels

Investigation on the charge drain mechanism:

Dark current VS Gate voltage at high TID

1.E-16

1.E-15

1.E-14

1.E-13

1.E-12

1.E-11

0.001

0.01

0.1

1 D

ark

Current

(

A)

Dose (MGy(SiO

₂

))

Pre Rad

1E-14

1E-13

1E-12

1E-11

-1 -0.5 0 0.5 1 1.5 2

D

a

rk

C

urrent

(

A)

Gate Voltage (V)

1 MGy, @22°C

(29)

Gate Overlap

and N

+

_Drain

RST N+ N+

SCR

STI

N CIS

P

P- _substrate

P

d

Gate Overlap

N CIS

RST N+ N+

SCR

N CIS

P

N +

d

STI

Gate Overlap

and N

+

_Drain



At TID > 10 Mrad

dark current decreases

with the increase of

gate voltage in both pixels



The charge drain mechanism is active in gate overlap design

because of the

STI inversion

Investigation on the charge drain mechanism:

Dark current VS Gate voltage at high TID

1.E-16

1.E-15

1.E-14

1.E-13

1.E-12

1.E-11

0.001

0.01

0.1

1 D

ark

Current

(

A)

Dose (MGy(SiO

₂

))

Pre Rad

1E-14

1E-13

1E-12

1E-11

-1 -0.5 0 0.5 1 1.5 2

D

a

rk

C

urrent

(

A)

Gate Voltage (V)

1 MGy, @22°C

(30)



3T Partially pinned photodiode is more radiation tolerant

than standard 3T photodiode for TID < 1 Mrad



P

+

_{layer limits the Si/SiO}

2 contact



At

TID > 1 Mrad

partially pinned functionality is lost

Sum up 2/2:

Pixel design influence

1.E-16

1.E-15

1.E-14

1.E-13

1.E-12

1.E-11

0.001

0.01

0.1

1 D

a

rk

C

urrent

(

A)

Dose MGy

Gate Overlap

and N

+

_Drain

Partially Pinned

Gate Overlap

Gate Aligned

3T Standard

Pixel

Pre Rad



Gate overlap design

gives best performances in

term of dark current for

positive voltages

applied

to the gate:



Gate overlap has to be optimized



N

+

_{Drain biased at VDD allow to control dark}

charges draining mechanisms

(31)



The manufacturing process

has an

important impact

on the

absolute radiation hardness of CIS



MOSFET performances



Dark Current



The gate overlap design is required

for TID beyond 100 Mrad



Optimization of Gate overlap



Influence of N

+

_{Drain size on optoelectrical performances}



The charge drain mechanism is

confirmed thanks to

VDD N+ drain design

Conclusions and perspectives

0

0.2

0.4

0.6

0.8 0.00010.001 0.01 0.1

1 M

OSFET

V

th

Shift

(

V

)

Dose (MGy(SiO

₂

))

Foundry C [5]

Foundry A

Foundry B

Pre Rad

Further development:



Integration of all the functions

in a single HD sensor

(ADC, Sequencer…)



Exploration of

other radiation conditions

to evaluate the

radiation response of these CISs (Charged particles,

Neutrons… )

for future spatial applications

such as Jupiter

Missions

100 Mrad

Only Gate overlap

designs are functional

(32)

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l’Espace

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