A 16-bit Linear Feedback Shift Register signature analyzer is placed on the Video output bus to compress the video data stream into a single signature that is output onto the Video Data pins during BLANK time. The Signature is also readable by the CPU at the end of a Frame using the DUMP_REG command at Register ID 3C (Read register 3D). This signa-ture analyzer output onto the VDAT A pins is activated in'DP Test Mode.
3.8.1 Invoking Test Mode
Test Mode is invoked at Reset by driving the RD, WR and MIO pins to the "Test Mode Select" states. These states are sampled by the 82786 when RESET goes inactive. The particular test mode selected is given in the following table:
RD# WR# MIO Mode
0 0 0 RESERVED
0 0 1 RESERVED
0 1 0 DP Test Mode
0 1 1 Force all outputs High
1 0 0 Force all outputs Low
1 0 1 Tristate all outputs
1 1 X Normal Operation
Once in DP Test Mode, the Signature Analyzer output is enabled by setting bit 14 of the DP Opcode register to 1. (See diagram below.)
15 14 13 12 11 10 9 8 7 6 5 4 3 2
o
I-I
S OPCODESignature Analyzer Output Enable (bit 14)
The remaining bits of the Opcode are still usable as in normal mode, and may be programmed to execute all DP instructions. In Normal Mode, setting bit 14 constitutes an Illegal Opcode, and is trapped as such. The DP will not execute the command, the Reserved Command Status Bit will set, and the DP will continue to operate as before the command had been given.
3.8.2 Operation of the Signature Analyzer
The Signature Analyzer sits on the video data output bus and accumulates the signature during active display time. Outgoing video data is sampled by the signature accumulator which generates a new signature each video clock cycle. At the end of each scan line the signature is output on the video data pins according to the following logic:
IF blank AND hsync# THEN
video_data: = 8 LSB of the signature.
IF blank AND hsync THEN
video_data: = 8 MSB of the signature.
The signatures from each line are accumulated and the signature of the complete screen is available at the beginning of the VBLANK time. The signature is then cleared on falling VSYNC. In this way there will be a unique signature for each display frame configuration.
If the display remains the same for many frames, or if there are certain standard test frames, their signatures will always be the same from one frame to the next, and from one device to
DISPLAY PROCESSOR OVERVIEW
the next. If something changes in the fame-a window is moved or deleted, or a change in the bitmap occurs-the final signature will be different. This allows the signature to be checked at the end of each frame (during VSYNC) for a coarse check on the goodness of the device or system.
The signature is readable by the CPU at the end of a frame using a DUMP_REG command.
This is useful as a coarse test to allow the CPU to "watch" the screen when performing a system self-check as part of a diagnostic check. The system may be set up to output a set of test patterns, and the CPU can check the DP signature register at the end of each frame to ensure that the correct signature has been generated.
The signature is not cleared between display lines. If it were, then the final signature would only reflect the goodness of the last display line, and the signatures would have to be checked on every display line. Signatures are accumulated over an entire frame, with the effect that two identical display lines on the same screen will yield two different signatures, since the signature is a result of all the preceding lines.
Video Data is output normally from the Video Data pins in Test Mode exactly as in Normal Mode. The only difference is that during BLANK in Normal Mode, Default Video is output to allow the user to address the Color Palette via the Default Video register, whereas in Test Mode the signature is output during BLANK.
Note that the Signature Analyzer accumulator is always enabled internally regardless of whether the DP is in Test Mode. The Signature Anlayzer Accumulator may therefore be read out by the CPU even in non-test mode and will give useful output. Test Mode simply enables the result of the Signature Anlayzer to be output onto the VDATA pins during BLANK. The value output onto the VDAT A pins will be the same value as is read by the
CPU. .
The Signature Analyzer is implemented using a 16-bit LFSR that generates the primitive polynomial:
A 16-bit LFSR gives a much betterfault coverage than a simpler 8-bit LFSR, but even so, there is a significant chance of an error in a typcial display screen, which may contain a quarter-million pixels or more, going undetected. To reduce this error rate, the signature may be checked every display line at the VDATA pins in Test Mode. Note also that the signature only accumulates Video Data that exits on the VDATA pins-in pure VRAM systems the video data does not pass through the 82786, so the signature analyzer will not accumulate this data.