STCK [S]
IB2 0S1 °2
o 16 20 31
The current value of the time-of-day clock is stored at the eight-byte field designated by the
second-operand address, provided the clock is in the set or not-set state.
Zeros are stored for the rightmost bit positions that are not provided by the clock.
Zeros are stored at the operand location when the clock is in the error state or in the
not-operational state.
The quality of the clock value stored by the instruction is indicated by the resultant
condition-code setting.
A serialization function is performed before the value of the clock is fetched and again after the value is placed in storage. CPU operation is delayed until all previous accesses by this CPU to
( I
~
storage have been completed, as observed by channels and other CPUs, and then the value of the clock is fetched. No subsequent instructions or their operands are fetched by this CPU until the clock value has been placed in storage, as observed by channels and CPUs.
Resulting Condition Code:
°
Clock in set state 1 Clock in not-set state 2 Clock in error state3 Clock in not-operational state Program Exceptions:
Access (store, operand 2) Programming Notes
1. Bit position 31 of the clock is incremented every 1.048576 seconds; hence, for timing applications involving human responses, the high-order clock word may provide sufficient resolution.
2. Condition code
°
normally indicates that the clock has been set by the control program.Accordingly, the value may be used in elapsed-time measurements and as a valid time-of-day and calendar indication. Condition code 1 indicates that the clock value is the elapsed time since the power for the clock was turned on. In this case the value may be used in elapsed-time measurements but is not a valid time-of-day indication. Condition codes 2 and 3 mean that the value provided by STORE CLOCK cannot be used for time measurement or indication.
3. If a problem program written for the
ECPS: VSE mode is to be run also on a model of System/370, then the program should take into account the fact that, on a model of System/370, the value stored when the
condition code is 2 or 3 is not necessarily zero.
STORE HALFWORD
STH R1,02(X2,B2) [RX]
'40'
I
R1I
X2I
B2 °20 8 12 16 20 31
Bits 16-31 of the general register designated by the Rl field are placed unchanged at the
second-operand location. The second operand is two bytes in length.
Condition Code: The code remains unchanged.
Program Exceptions:
Access (store, operand 2) STORE MULTIPLE
STM [RS]
'90'
o 8 12 16 20 31
The contents of the set of general registers starting with the register specified by R 1 and ending with the register specified by R3 are placed in the storage area beginning at the location designated by the second-operand address and continuing through as many locations as needed.
The general registers are stored in the ascending order of register numbers, starting with the register specified by R 1 and continuing up to and including the register specified by R3, with register
°
following register 15. .
Condition Code: The code remains unchanged.
Program Exceptions:
Access (store, operand 2) Programming Note
An example of the use of STORE MULTIPLE is given in Appendix A.
SUBTRACT
SR [RR]
'lB'
I
R1I
R2I
o 8 12 15
S R1,02(X2,B2) [RX]
'SB'
I
R1I
X2I
B2 °20 8 12 16 20 31
The second operand is subtracted from the first operand, and the difference is placed in the first-operand location. The operands and the difference are treated as 32-bit signed binary integers.
Chapter 7. General Instructions 7-33
An overflow causes a program interruption when the fixed-point-overflow mask bit is one.
Resulting Condition Code:
o
Difference is zero1 Difference is less than zero 2 Difference is greater than zero 3 Overflow
Program Exceptions:
Access (fetch, operand 2 of S only) Fixed-Point Overflow
Programming Notes
1. When, in the RR format, the R 1 and R2 fields designate the same register, subtracting is equivalent to clearing the register.
2. Subtracting a maximum negative number from another maximum negative number gives a zero result and no overflow.
SUBTRACT HALFWORD
SH [RX]
148 I
I
R 1I
X2I
82o
8 12 16 20 31The second operand is subtracted from the first operand, and the difference is placed in the first-operand location. The second operand is two bytes in length and is treated as a 16-bit signed binary integer. The first operand and the difference are treated as 32-bit signed binary integers.
An overflow causes a program interruption when the fixed-point-overflow mask bit is one.
Resulting Condition Code:
o
Difference is zero1 Difference is less than zero 2 Difference is greater than zero 3 Overflow
Program Exceptions:
Access (fetch, operand 2) Fixed-Point Overflow
SUBTRACT LOGICAL
SLR R1,R2 [RR]
I 1 F I
I
R1I
R2I
o 8 12 15
7-34 IBM 4300 Processors Principles of Operation
o 8 12 16 I 20 31
The second operand is subtracted from the first operand, and the difference is placed in the first-operand location. The operands and the difference are treated as 32-bit unsigned binary integers.
Resulting Condition Code:
o
1 Difference is not zero, with no carry 2 Difference is zero, with carry 3 Difference is not zero, with carry Program Exceptions:
Access (fetch, operand 2 of SL only) Programming Notes
1. Logical subtraction is performed by adding the one's complement of the second operand and a low-order one to the first operand. The use of the one's complement and the low-order one instead of the two's complement of the second operand results in a carry when subtracting zero.
2. SUBTRACT LOGICAL differs from SUBTRACT only in the meaning of the condition code and in the absence of the interruption for overflow.
3. A zero difference is always accompanied by a carry out of the high-order bit position.
4. The condition-code setting for SUBTRACT LOGICAL can also be interpreted as indicating the presence and absence of a borrow, as follows:
1 Difference is not zero, with borrow 2 Difference is zero, with no borrow 3 Difference is not zero, with no borrow
SUPERVISOR CALL
SVC [RR]
'OA'
o 8 15
The instruction causes a supervisor-call interruption, with the I field of the instruction providing the interruption code.
Bits 8-15 of the instruction, with eight high-order zeros appended, are placed. in the supervisor-call interruption code that is stored in the course of the interruption. See
"SupervisQr-Call Interruption" in Chapter 6,
"Interruptions. "
A serialization function is performed. CPU operation is delayed until all previous storage accesses by this CPU to storage have been
completed, as observed by channels and and other CPUs. No subsequent instructions or their
operands are accessed by this CPU until the execution of this instruction is completed.
Condition Code: The code remains unchanged and is saved as part of the old PSW. A new condition code is loaded as part of the supervisor-call interruption.
Program Exceptions: None.