On all machine-check interruptions, a
machine-cheek-interruption code (MCIC) is stored at the doubleword starting at location 232 and has the format shown in the figure "Machine-Check Interruption-Code Format."
Bits in the MCIC which are not assigned, or not implemented by a particular model, are stored as zeros.
Chapter 11. Machine-Check Handling 11-7
I ~
P S T C E D S K W M P I F FG C S D R D D D 0 G WOO 0 0 0 0 D Eo
E 0 PS M A Ao
0 P R ROTo 9 15 20 27 31
o
0 000 0 0 0 0 0 0 000 000 0 0 0 0 0 000 000 0 032 46 48 63
Bits Name
o
System damage (SD)1 Instruction-processing damage (PD) 2 System recovery (SR)
3 Interval-timer damage (TD) 4 Timing-facility damage (CD) 5 External damage (ED)
7 Degradation (DG) 8 Warning (W) 15 Delayed (D)
16 Storage error uncorrected (SE) 18 Storage-key error uncorrected (KE) 20 PSW-EMWP validity (WP)
21 PSW mask and key validity (MS)
22 PSW program-mask and condition-code validity (PM) 23 PSW-instruction-address validity (IA)
24 Failing-storage-address validity (FA) 27 Floating-point-register validity (FP) 28 General-register validity (GR)
29 Control-register validity (CR) 31 Storage logical validity (ST) 46 CPU-timer validity (CT)
47 Clock-comparator validity (CC)
Note: All other bits of the MCIC are unassigned and stored as zeros.
Machine-Check Interruption-Code Format
Programming Note
The program should not depend on unassigned bits in the machine-cheek-interruption code being zeros, so as to ensure that existing programs run if and when new facilities using these bits are defined.
Subclass
Bits 0-5, 7, and 8 are the subclass bits which identify the type of machine-check condition causing the interruption. At least one of the subclass bits is stored as a one. When multiple errors have occurred, several of the defined bits may be set to ones.
11-8 IB M 4300 Processors Principles of Operation
System Damage
Bit 0 (SD), when one, indicates that damage has occurred which cannot be isolated to one or more of the less severe machine-check subclasses. When system damage is indicated, the remaining bits in the machine-cheek-interruption code are not meaningful, and information stored in the register-save areas a:gd failing-storage-address field is not meaningful. System damage is an exigent
condition.
Instruction-Processing Damage
Bit 1 (PD), when one, indicates that damage has occurred to the instruction processing of the CPU.
For damage to be indicated as instruction~
pr:ocessing damage, the point of damage and the.
point· of interruption must not be separated by an interruption or by a LOAD PSW instruction and the damaged entity must be due to be changed by the current instruction.
Instruction-processing damage is an exigent condition.
System Recovery
Bit 2 (SR), when one, indicates that malfunctions were detected but did not result in damage or have been successfully corrected. Some malfunctions detected as part of an 110 operation may result in a system-recovery condition in addition to an I/O-error condition. The presence and extent of the system-recovery capability depend on the model.
System recovery is a repressible condition.
Programming Notes
1. System recovery may be used to report a failing-storage address detected by a CPU prefetch or by an I/O operation.
2. Unless the corresponding validity bits are ones, the indication of system recovery does not imply storage logical validity, or that the fields stored as a result of the machine-check interruption are valid.
Interval-Timer Damage
Bit 3 (TD), when one, indicates that damage has occurred to the interval timer or to storage location 80. Interval-timer damage is a repressible
condition.
Timing-Facility Damage
Bit 4 (CD), when one, indicates that damage has occurred to the time-of-day clock, the CPU timer, the clock comparator, or to the CPU-timer or clock-comparator external-interruption conditions.
The timing-facility-damage machine-check condition is set whenever any of the following occurs:
1. The time-of-day clock enters the error or not-operational state.
2. The CPU timer is damaged, and the CPU is enabled for CPU-timer external interruptions.
Depending on the model, the machine-check condition may be generated only as the CPU timer enters an error state. Or, the
machine-check condition may be continuously
generated whenever the CPU is enabled for CPU-timer interruptions, until the CPU timer is validated.
3. The clock comparator is damaged, and the CPU is enabled for clock-comparator external
interruptions.
Timing-facility damage may also be set along with instruction-processing damage when an instruction which accesses the CPU timer or clock comparator produces incorrect results.
Timing-facility damage is a repressible condition.
Programming Note
Timing-facility-damage conditions for the CPU timer and the clock comparator are not recognized when these facilities are not in use. The facilities are considered not in use when the CPU is disabled for the corresponding external interruptions (PSW bit 7, or the subclass-mask bits~ bits 20 and 21 of control register 0, are zeros), and when the corresponding set and store instructions are not being issued. Timing-facility-damage conditions that are already pending remain pending, however, when the CPU is disabled for the corresponding external interruption.
Timing-facility-damage conditions due to damage to the time-of-day clock are always recognized.
External Damage
Bit 5 (ED), when one, indicates that damage has occurred to a channel or to storage during
operations not directly associated with processing the current instruction. Channel malfunctions are reported as external damage only when the channel is unable to report the malfunctions by an
I/O-error condition. Depending on the model and on the type and extent of the error, an
external-damage condition may be indicated as system damage instead of external damage.
External damage is a repressible condition.
Degradation
Bit 7 (DG), when one, indicates that continuous degradation of system performance, more serious than that indicated by system recovery, has occurred. Degradation may be reported when system-recovery conditions exceed a machine-preestablished threshold. The presence and extent of the degradation-report capability depends on the model.
Degradation is a repressible condition.
Chapter 11. Machine-Check Handling 11-9
Warning
Bit 8 (W), when one, indicates that damage is imminent in some, part of the system (for example, that power is about to fail, or that a loss of cooling is occurring). Whether warning conditions are recognized depends on the model.
If the condition responsible for the imminent damage is removed before the interruption request is honored (for example, if power is restored), the request does not remain pending, and no
interruption occurs. Conversely, the request is not cleared by the interruption, and, if the condition persists, more than one interruption may result from the same condition.
Warning is a repressible condition.