The following rules govern the indication of PER events caused by an instruction that has also caused a program exception or the monitor event to be indicated, or that causes a supervisor-call interruption.
1. The indication of an instruction-fetching event does not depend on whether the execution of the instruction was completed, terminated, suppressed, or nullified. The event, however, is not indicated when an access exception
prohibits access to the first byte of the instruction. When the first halfword of the instruction is accessible but an access exception
applies to the second or third halfword of the instruction, it is unpredictable whether the instruction-fetching event is indicated.
2. When the operation is completed, the event is indicated regardless of whether any program exception or the monitoring event is
recognized.
3. Successful branching, storage alteration, and general-register alteration are not indicated for an operation or, in case the instruction is interruptible, for a unit of operation that is suppressed or nullified.
4. When the execution of the instruction is terminated, general-register or storage
alteration is indicated whenever the event has occurred, and a model may indicate the event if the event would have occurred had the
execution of the instruction been completed, even if altering the contents of the result field is contingent on operand values.
5. When LOAD PSW or SUPERVISOR CALL causes a PER condition and at the same time introduces a new PSW with the type of PSW-format error that is recognized
immediately after the PSW becomes active, the interruption code identifies both the PER condition and the specification exception.
When these instructions introduce a
PSW-format error of the type that is recognized as part of the execution of the following
instruction, the PSW is stored as the old PSW without the specification exception being recognized.
The indication of PER events concurrently with other program interruption conditions is
summarized in the figure "Indication of PER Events. "
Chapter 4. Control 4-13
PER Event
Type Storage GR
of Instr A 1 tet- Alter-Exception Ending Branch Fetch ation ation
Operation S - Xl -
-Privileged operation S - Xl -
-Execute S - Xl
-
-p'rotect ion
Instruction S - _1
-
-Operand S or T - X X+ X+
Addressing
Instruction S
-
_1 --Operand S or T
-
X X+ X+Specification
Odd instruction address S
-
- --Invalid PSW format C - X -
-Other S - X
-
-Data
Invalid sign S - X
-
-Other T
-
X X+ X+Fixed-po int overflow C
-
X - XFixed-point divide
Division S - X -
-Conversion C
-
X - XDecimal overflow C - X X
-Decimal divide S - X
-
-Exponent overflow C
-
X --Exponent underf10w C
-
X --Significance C - X
-
-Float ing-po i nt divide S - X -
-Special operation S - X -
-Page access
Instruction N
-
_1 --Operand N
-
X X2 X2Page state S - X -
-Page transition S
-
X-
-, Mon i tor event C - X -
-Indication of PER Events (Part 1 of 2)
4~14 IBM 4300 Processors Principles of Operation
Explanation:
C The operation or, in the case of the interruptible instructions, the unit of operation is completed.
N The operation or, in the case of the interruptible instructions, the unit of operation is nullified. The instruction address in the old PSW has not been updated.
S The operation or, in the case of the interruptible instructions, the unit of operation is suppressed.
T The execution of the instruction is terminated.
X The event is indicated with the exception if the event has occurred; that is, the contents of the monitored storage location or general register were altered, or an attempt was made to execute an instruction whose first byte is located in the monitored area.
+ A model is permitted, but not required, to indicate the event if the event would have occurred had the operation been completed but did not take place because the execu-tion of the instrucexecu-tion was terminated.
2
The event is not indicated.
When an access exception applies to the second or third halfword of the instruction but the first halfword is accessible, it is unpredictable whether the instruction-fetcning event is indicated.
This condition may occur in the case of the interrupt-ible instructions when the event is recognized in the unit of operation that is completed and when the excep-tion causes the next unit of operaexcep-tion to be suppressed or null ified.
Indication of PER Events (Part 2 of 2)
Programming Notes
1. The execution of the interruptible instructions MOVE LONG (MVCL) and COMPARE LOGICAL LONG (CLCL) can cause events for general-register alteration and instruction fetching. Additionally, MVCL can cause the storage-alteration event.
a. The instruction-fetching event is indicat(
whe'never the instruction is fetched for execution, regardless of whether it is the initial execution or a resumption.
Since the execution of MVCL and CLCL can be interrupted, a program event may be indicated more than once. It may be necessary, therefore, for a program to remove the
redundant event indications from the PER data.
The following rules govern the indication of the applicable events during execution of these two instructions:
b. The general-register-alteration event is indicated on the initial execution and on each resumption and does not depend on whether or not the register actually is changed.
c. The storage-alteration event is indicated only when data has been stored in the monitored area by the portion of the operation starting with the last initiation and ending with the last byte transferred
Chapter 4. Control 4-15
before the interruption. No special indication is provided on premature interruptions as to whether the event will occur again upon the resumption of the operation. When the storage area designates a single byte location, a
storage-alteration event can be recognized only once in the execution of MOVE LONG.
2. The following is an outline of the general action a program must take to delete the redundant entries in the PER data for MOVE LONG and COMPARE LOGICAL LONG so that only one entry for each complete execution of the instruction is obtained:
a. Check to see if the PER address is equal to the instruction address in the old PSW and if the last instruction executed was MVCL or CLCL.
b. If both conditions are met, delete
instruction-fetching and register-alteration events.
c. If both conditions are met and the event is storage alteration, delete the event if some part of the remaining destination operand is within the monitored area.