ADD UNNORMALIZED

[RR, Short Operands]

o 8 12 15

AU [RX, Short Operands]

o 8 12 16 20 31

[RR, Long Operands]

o 8 12 15

AW R1,D2(X2,B2) [RX, Long Operands]

I 6E ^I

I

^{R 1}

I

^X2

I

^{B2 D2}

o 8 12 16 20 31

The second operand is added to the first operand, and the unnormalized sum is placed in the

first-operand location.

The execution of ADD UNNORMALIZED is identical to that of ADD NORMALIZED, except that:

1. When no carry is· present after the addition, the intermediate-sum fraction is truncated to the proper result-fraction length without a left shift to eliminate leading hexadecimal zeros and without the corresponding reduction of the characteristic.

2. Exponent underflow cannot occur.

3. The guard digit does not participate in the recognition of a zero result fraction. A zero result fraction is recognized when the fraction, that is, the intermediate-sum fraction, excluding the guard digit, is zero.

The R 1 and R2 fields must designate register 0, 2, 4, or 6; otherwise, a specification exception is recognized.

Resulting Condition Code:

o

Result fraction is zero 1 Result is less than zero 2 Result is greater than zero 3

Program Exceptions:

Access (fetch, operand 2 of AU and AW only) Exponent Overflow

Significance Specification Programming Note

Except when the result is made a true zero, the characteristic of the result of ADD

UNNORMALIZED is equal to the greater of the two operand characteristics, increased by one if the fraction addition produced a carry.

Chapter 9. Floating-Point Instructions 9-7

COMPARE

[RR, Short Operands]

o

8 12 15

CE [RX, Short Operands]

179 ^I

I

^{R 1}

I

^X2

I

^B2

o 8 12 16 20 31

CDR [RR, Long Operands]

o 8 12 15

CD [RX, Long Operands]

169 ^I

I

^{R 1}

I

^X2

I

^B2

o 8 12 16 20 31

The first operand is compared with the second operand, and the condition code is set to indicate the result.

The comparison is algebraic and follows the procedure for normalized floating-point

subtraction, except that the difference is discarded after setting the condition code and both operands remain unchanged. When the difference, including the guard digit, is zero, the operands are equal.

When a nonzero difference is positive or negative, the first operand is high or low, respectively.

An exponent-overflow, exponent-underflow, or significance exception cannot occur.

The Rl and R2 fields must designate register 0, 2, 4, or 6; otherwise, a specification exception is recognized.

Resulting Condition Code:

°

Operands are equal 1 First operand is low 2 First operand is high 3

Program Exceptions:

Access (fetch, operand 2 of CE and CD only) Specification

9-8 IBM 4300 Processors Principles of Operation

Programming Notes

1. An exponent inequality alone is not sufficient to determine the inequality of two operands with the same sign, because the fractions may have different numbers of leading hexadecimal zeros.

2. Numbers with zero fractions compare equal even when they differ in sign or characteristic.

DIVIDE

[RR, Short Operands]

o

8 12 15

DE R1,D2(X2,B2) [RX, Short Operands]

I 7D ^I

I

^{R 1}

I

^X2

I

^B2

I

^D2

o 8 12 16 20 31

[RR, Long Operands]

o 8 12 15

DD R1,D2(X2,B2) [RX, Long Operands]

I 6D ^I

I

^{R 1}

I

^X2

I

^B2

I

^D2

o 8 12 16 20 31

The first operand (the dividend) is divided by the second operand (the divisor), and the normalized quotient is placed in the first-operand location. No remainder is preserved.

Floating-point division consists in characteristic subtraction and fraction division. The operands are first normalized to eliminate leading hexadecimal zeros. The difference between the dividend and divisor characteristics of the normalized operands, plus 64, is used as the characteristic of an

intermediate quotient.

All dividend and divisor fraction digits participate in forming the fraction of the

intermediate quotient. The intermediate-quotient fraction can have no leading hexadecimal zeros, but a right-shift of one digit position may be necessary ~ ^/

with an increase of the characteristic by one. The fraction is then truncated to the proper result-fraction length.

An exponent-overflow exception is recognized when the characteristic of the final quotient would exceed 127 and the fraction is not zero. The operation is completed by making the characteristic 128 less than the correct value. The result is normalized, and the sign and fraction remain correct. A program interruption for exponent overflow occurs.

An exponent-underflow exception exists when the characteristic of the final quotient would be less than zero and the fraction is not zero. If the exponent-underflow mask bit is one, the operation is completed by making the characteristic 128 greater than the correct value, and a program interruption for exponent underflow occurs. The result is normalized, and the sign and fraction remain correct. If the exponent-underflow mask bit is zero, a program interruption does not take place; instead, the operation is completed by making the quotient a true zero.

Exponent underflow does not occur when an operand characteristic becomes less than zero during normalization of the operands or when the intermediate-quotient characteristic is less than zero, as long as the final quotient can be represented with the correct characteristic.

When the divisor fraction is zero, the operation is suppressed, and a program interruption for floating-point divide occurs. This includes the division of zero by zero.

When the dividend fraction is zero, but the divisor fraction is nonzero, the quotient is made a true zero. No exponent overflow or exponent underflow occurs.

The sign of the quotient is determined by the rules of algebra, except that the sign is always plus when the quotient is made a true zero.

The Rl field for DER, DE, DDR, and DD, and the R2 field for DER and DDR, must designate register 0, 2, 4, or 6. Otherwise, a specification exception is recognized.

Condition Code: The code remains unchanged.

Program Exceptions:

Access (fetch, operand 2 of DD and DE only) Exponent Overflow

Exponent Underflow Floating-Point Divide Specification

HALVE

[RR, Short Operands]

o ^{8 12 15}

[RR, Long Operands]

o

8 12 15

The second operand is divided by 2, and the normalized quotient is placed in the first-operand location.

The fraction of the second operand is shifted right one bit position, placing the contents of the rightmost bit position into the leftmost bit position of the guard digit and introducing a zero into the leftmost bit position of the fraction. The

intermediate result, including the guard digit, is then normalized, and the final result is truncated to the proper length.

An exponent-underflow exception exists when the characteristic of the final result would be less than zero and the fraction is not zero. If the exponent-underflow mask bit is one, the operation is completed by making the characteristic 128 greater than the correct value, and a progratp.

interruption for exponent underflow occurs. The result is normalized, and the sign and fraction remain correct. If the exponent-underflow mask bit is zero, a program interruption does not take place; instead, the operation is completed by making the result a true zero.

When the fraction of the second operand is zero, the result is made a true zero, and no exponent underflow occurs.

The sign of the result is the same as that of the second operand, except that the sign is always plus when the quotient is made a true zero.

The R 1 and R2 fields must designate register 0, 2, 4, or 6; otherwise, a specification exception is recognized.

Condition Code: The code remains unchanged.

Program Exceptions:

Exponent Underflow Specification

Chapter 9. Floating-Point Instructions 9-9

Programming Notes

1. With short and long operands, the halve

operation is identical to a divide operation with the number 2 as divisor. Similarly, the result of HDR is identical to that of MD or MDR with one-half as a multiplier. No multiply operation corresponds to HER, since no multiply

operation produces short results.

The result of HALVE is zero only when the second-operand fraction is zero, or when exponent underflow occurs with the exponent-underflow mask set to zero. A fraction with zeros in every bit position, except for a one in the rightmost bit position, does not become zero after the right shift. This is because the one bit is preserved in the

guard-digit position and becomes the leftmost bit after normalization of the result.

LOAD

[RR, Short Operands]

o 8 12 15

LE [RX, Short Operands]

o 8 12 16 20 31

LOR R1,R2 [RR, Long Operands]

1281 R1 R2

o 8 12 15

LO [RX, Long Operands]

o

8 12 16 20 31

The second operand is placed unchanged in the first-operand location.

The

R

1 and R2 fields must designate register 0, 2, 4, or 6; otherwise, a specification exception is recognized.

Condition Code: The code remains unchanged.

9-10 IB M 4300 Processors Principles of Operation

Program Exceptions:

Access (fetch, operand 2 of LE and LD only) Specification

LOAD AND TEST

[RR, Short Operands]

o 8 12 15

[RR, Long Operands]

o

8 12 15

The second operand is placed unchanged in the first-operand location, and its sign and magnitude are tested to determine the setting of the condition code.

The R 1 and R2 fields must designate register 0, 2, 4, or 6; otherwise, a specification exception is recognized.

Resulting Condition Code:

°

Result fraction is zero 1 Result is less than zero 2 Result is greater than zero 3

Program Exceptions:

Specification Programming Note

When the same register is specified as the first-operand and second,...operand location, the operation is equivalent to a test without data movement.

LOAD COMPLEMENT

LeER R1,R2 [RR, Short Operands]

o

8 12 15

[RR, Long Operands]

o 8 12 15

The second operand is placed in the first-operand

I

location with the sign bit inverted.

The sign bit is inverted, even if the fraction is zero. The characteristic and fraction are not changed.

The R1 and R2 fields must designate register 0, 2, 4, or 6; otherwise, a specification exception is recognized.

Resulting Condition Code:

o

Result fraction is zero 1 Result is less than zero 2 Result is greater than zero 3

Program Exceptions:

Specification

Dans le document IBM 4300 Processors Principles of Operation for ECPS: VSE Mode (Page 150-154)