INPUT/OUTPUT AND CONTROL OPERATIONS
4.3 STANDARD IDee DOUBLE WORDS AI though the IOCC configurations are usually
tailored for each individual applica tion, certain standard configurations have been preassigned.
Standard IOCC double words have been preassigned for the following operations:
a. Start/stop interval timers b. Sense interval timers
c. Sense console data switches d. Read console data switches e. Mask/unmask interrupt levels f. Set program interrupt register g. Sense interrupt level status word h. Sense console interrupt status word 1. Reset operations monitor alarm
j. Initialize Teletype or inhibit direct memory transfer
These operations are specified by laCe's with an area code of zero and bits 8 through 10 of the modi-fier field designating the operation as shown in the following descriptions:
START/STOP INTERVAL TIMERS
J
o 1 2 3 4 5 6 7 8 9 1011 121314150 1 2 3 4 5 6 7 8 9 101112131415
II.
LTIMER CTIMER B TIMER A
88A00026A
This Ioee is used to start or stop the inteIVal timers. Bits 0 through 2 designate timer A (memory locationXl00041), timerB (memory locationX ' 00051) , and timer C (memory location XI 0006 1), respectively.
A I-bit in the designated bit position starts the corresponding timer operating; a O-bit stops the timer. For detailed information on inteIVal timer operation, see paragraph 2. 19.
SENSE INTERVAL TIMERS STATUS WORD
o 1 2 3 4 5 6 7 8 9 1011 12131415 0 1 2 3 4 5 6 7 8 9 1011 12131415 0- RESET DSW INDICATOR}~
1 - DO NOT RESET DSW INDICATOR
This IOee copies the device status word (DSW) for the inteIVal timers into the accumulator. The format of the status word is as follows:
o 1 2 3 4 5 6 7 8 9101112131415
/' L
TIMER C TIMER B TIMER ABits 0 through 2 of the DSW identify the timer requesting the interrupt. A I-bit indicates that an interrupt has been requested by the correspond-ing timer. Modifier bit 15 of the IOee specifies whether the DSW indicators are reset as the status word is copied into the accumulator. They are reset if modifier bit 15 contains a 1. The previous contents of the accumulator are destroyed by this
IOee.
SENSE CONSOLE DATA SWITCHES
o 1 2 3 4 5 6 7 8 9101112131415 0 1 2 3 4 5 6 7 8 9 101112131415
This IOee copies the status of console data switches 0 through 15 into the correspondingly numbered bit positions of the accumulator. The previous contents of the accumulator are destroyed.
READ CONSOLE DATA SWITCHES
ADDRESS AREA FUN MODIFIER
~---p---~----~---MEMORY ADDRESS
o 1 2 3 4.5 6 7 8 9 1011121314150 1 2 3 4 5 6 7 8 9 1011 12131415
This IOee stores the status of console data
switches 0 through 15 at the memory location speci-fied by IOee 1. The contents of the accumulator are not affected.
INITIALIZE TELETy.pE OR INHIBIT DIRECT MEMORY TRANSFER
o 1 2 3 4 5 6 7 8 9 101112131415 0 1 2 3 4 5 6 7 8 9 101112131415
III LINHIBIT DIRECT MEMORY TRANSFER
L
RECEIVE ONLY RECEIVE AND ECHO TRANSMITThis IOee is used to prepare the Teletype for transmitting or receiving data (with or without echo) or to inhibit direct memory transfer operations, as specified by bits 0 through 3 of IOee 1. A I-bit in any of these bit positions causes the specified operation. The operation is undefined if a 1 appears in more than one of the bit positions 0, 1 or 2.
MASK/UNMASK INTERRUPT LEVELS
ADDRESS AREA FUN MODIFIER
INTERRUPT LEVELS
! I , , I , I , I I , , ,
o 1 2 3 4 5 6 7 8 9 1011 121314150 1 2 3 4 5 6 7 8 9 1011 12131415
0 " THRU - 1 3
14 II THRU ..
30 .. THRU ..
46 - - - THRU - - 58
'--"'
} {
LEVELS OTHRU 13-000 29 _ LEVELS 14 THRU 29 - 0 0 1 45 LEVELS 30 THRU 45 - 0 1 1 LEVELS 46 THRU 58 - 1 0 1
This IOee is used to mask or unmask the external interrupt levels (internal and trace interrupts cannot be masked). The status of bit positions 0 through 13 I
o
through 15, or 0 through 12 of IOee I, depending on modifier bits 13 through 15 I are copied into the interrupt mask register. Each bit position represents4-3
88A00026A one interrupt level, and the status of the bit specifies whether the level is masked (1) or unmasked (0).
The level represented by each bit position is deter-mined by modifier bits 13 through 15 as follows:
When an interrupt level is masked (corresponding bit position of IOeel contains a 1), all interrupt requests on that interrupt level are prevented from being acknowledged until another IOee is executed to unmask the level. All external interrupt levels are automatically masked when the RESET switch on the programmer's console is pressed.
This laCe triggers an external interrupt or interrupts from within the program by setting the program infor-mation even though the interrupt mask register is
4-4
set. It is therefore pos'sible to set a programmed interrupt at an interrupt level which is masked or becomes masked before the interrupt occurs. Subse-quently, when the interrupt level becomes unmasked, the programmed interrupt will occur.
The level represented by each bit position of the PIR is exactly the same as in the Mask/Unmask Interrupt Levels laCe. The specified interrupt levels are triggered only if they are unmasked and do not become masked before the forced interrupt BSI instruction is executed. Since this command triggers the interrupt level itself and !"lot an individual interrupt, no bits are turned on in the interrupt level status word. For detailed information on interrupt operation, see para-graph 4. 10.
NOTE
For correct operation the program-triggered interrupt must be allowed to occur as soon as possible since no other interrupts can occur in the meantime.
SENSE INTERRUPT LEVEL STATUS WORD
o 1 2 3 4 5 6 7 8 9 101112131415 0 1 2 3 4 5 6 7 8 9 101112131415
This laCe copies the status word for the highest priority interrupt level requesting service into the accumulator. The status of the indicators in the devices assigned to the ILSW are not reset. The previous contents of the accumulator are destroyed by this laCe.
SENSE CONSOLE INTERRUPT STATUS WORD
0123456789101112131415,0123456789101112131415
88A00026A Paragraphs 4.4 to 4.6
RESET OPERATIONS MONITOR ALARM (STALL ALARM) AREA FUN MODIFIER
o 1 2 3 4 5 6 7 8 9 1011 12131415 0 1. 2 3 4 5 6 7 8 9 1011 12131415 0- TIMER NOT RESET}J
1 - TIMER RESET
This lace resets the stall alarm timer to zero each time it is executed with modifier bit 15 set to 1.
If bit 15 is set to 0 I the timer is not reset. For detailed information on the operation of the stall alarm I see paragraph 2.23.