3.1 GENERAL
This section describes the operations performed by the computer instructions. The instruction descrip-tions are grouped according to the following
functional classes:
a. Load and Store b. Arithmetic c. Shift d. Branch
e. Register Transfer
f. Input/Output and Control
The following format is used in describing each instruction:
MNEMONIC INSTRUCTION NAME TIMING
DESCRIPTION
OPERATION STATEMENT INDICATORS
AFFECTED
MNEMONIC. The mnemonic is the abbreviation that is recognized and used by the assembler to produce the unique operation code for each instruction.
INSTRUCTION NAME. The instruction name is the descriptive title of the instruction.
TIMING. Instruction execution time is given for the single word version of the instruction. An additional 1.2 microseconds should be added for double word
instructions I and another 1.2 microseconds I if the instruction specifies indirect addressing. For shift instructions the executiontime is given as
1.2 + 1.2 (N/4) microseconds I where N represents the number of shifts and N/4 must be an integer.
All special timing considerations, other than those specified here, are defined in the instruction descriptions.
FORMAT DIAGRAMS. The instruction format diagrams show the binary and hexadecimal configuration for both the single word and double word (if applicable) versions of each instruction. The upper half of the format shows the binary configuration; the lower half, the hexadecimal configuration. Both the binary and hexadecimal notations are shown for fields in which the contents are fixed. Abbrevia-tions or words are used to identify fields in which the contents are variable. The following abbrevi-ations are used in the format diagrams:
BO Branch out of interrupt flag COND Condition
F Format designator IA Indirect address flag N Number of shifts OP Operation code RD Destination register RS Source register
T Indexed addressing tag X Variable hexadecimal value
DESCRIPTION. The instruction description explains the operations performed by the computer in execut-ing the instruction.
OPERATION STATEMENT. The operation statement summarizes instruction operation in symbolic nota-tion or simplified diagrams wherever possible.
Symbolic terms and abbreviations used in the opera-tion statement are:
DISP Displacement (contents of bit posi-tions 8 through 15 of the instruction)
3-1
Paragraph 3.2 88A0002SA
EA
EDISP
( )
x
+
n u
>
<
Effective address. The effective address is the final IS-bit address value developed for the instruction after all address arithmetic has been perfonned
Expanded displacement. The value obtained when the displacement is automatically expanded to a IS-bit value by duplicating bit position 8
(sign bit) in bit positions 0 through 7 Contents of register or memory location specified
Multiplication Division Addition Subtraction
Logical product (AND) Logical sum (OR)
Logical comparison (exclusive OR) Greater than
Less than Equal
~ Replace
INDICATORS. The instruction's effect on the Carry and Overflow indicators is specified.
AFFECTED. All programmable registers and memory locations that can be affected by the instruction are listed.
3.2 LOAD AND STORE INSTRUCTIONS The following load and store instructions are available to the programmer:
LDS Load Status STS Store Status LDX Load Index STX Store Index LD Load Accumulator LDD Load Double
3-2
STO Store Accumulator STD Store Double
All of the instructions, with the exception of Load Status, can be used in either the single or double word fonnat. The Load Status instruction can be used only in the single word fonnat.
Indirect addressing can be specified for all of the double word instructions except Load Index.
Although the indirect address (IA) bit is used in this instruction, its interpretation is different from that of nonnal indirect addressing. The way in which this bit is used is explained in the descrip-tion of the Load Index instrucdescrip-tion.
LOS LOAD STATUS 1.21J.S
OP F T DISPLACEMENT
1
0 021 0O!O~O
010 000 0 0~;-I
I I I
I
I I I II
I Io 12 3 4 5 6 7 8 9101112131415
The Load Status instruction copies the status of bits 14 and 15 of its displacement field into the Carry and Overflow indicators. Bit 14 is copied into the Carry indicator, and bit 15 is copied into the Over-flow indicator. A I-bit turns the corresponding indicator on; a O-bit turns it off. The contents of Carry and Overflow are nonnally copied into the displacement field of the Load Status instruction by a Store Status instruction.
This instruction is a single-word instruction only.
Its displacement field is used only for changing the status of the Carry and Overflow indicators, not for memory addressing.
(DISP)14 ---.. (CARRY) (DISP) 15 - - (OVE RFLOW)
Indicators: Carry and Overflow are set or reset according to the states of displacement bits 14 and 15.
Affected: None
STS STORE STATUS 2.4 p,s
o 1 2 3 4 5 6 7 8 91011121314150 12 3 4 5 6 7 89101112131415
88A00026A
The Store Status instruction perfonns either of the following operations:
a. If the single word instruction is used, or if bit 9 (BO) of the double word instruction is zero, the status of the Carry and Overflow indicators is
stored in bit positions 14 and 15 of the location specified by the effective address. Carry status is stored in bit position 14; Overflow status, in bit position 15. The contents of bits 0 through 7 of the effective address remain unchanged, and bits 8 through 13 are reset to zero.
o 1 2 3 4 5 6 7 8 9101112131415 , UNCHANGED I CAR RY
-1 I
OVERFLOW
b. If bit 9 (BO) of the double word instruction is a I, the storage protection bit of the memory location specified by the effective address is set or cleared according to the status of condition bit 15, as follows:
Bit 15
o
1
Result
Clear storage protection bit Set storage protection bit
All other bits except the parity bit are unchanged.
The storage protection bits can be changed only when the WSPB switch on the control console is unlocked (otherwise, the instruction performs no operation). For this function, the ins truction requires 1.32 microseconds for execution.
For single word instruction or double word instruction with BO
=
0:(CARRY) - - - (EA)14 (OVERFLOW) - - - (EA) 15
O's--- (EA)8_13 For double word instruction with BO = 1:
Clear storage protection bit if bit 15 is 0 Set storage protection bit if bit 15 is 1 Indicators: Carry and Overllow are reset as they are stored.
Affected: (EA) 8-15
LOX LOAD INDEX 1.21-'5
F T
o 1 2 3 4 5 6 7 89101112131415 OP F T IA COND
ADDRESS
10 1 1 0
0~1 ~-1-10 0 0 0'0 0 01
, ~ , 14~7, 0 QR,81 ! Q ! ! ~ !
I ,
~, I
!.~ ,I .
~.
o 1 2 3 4 5 6 7 8 9 101112131415" 0 1 2 3 4 5 6 7 8 9 101112131415
The Load Index instruction loads the e){panded displacement, the address field, or the contents of the location specified by the address field into the register specified by the tag (T) field. The register is specified as follows:
T Register
00
01 XRl
10 XR2
11 XR3
When the single word instruction is used I the expanded displacement is loaded into the speCified register.
When the double word instruction is used I the IA bit of the instruction determines whether the con-tents of the address field or the concon-tents of the location specified by the address field are loaded into the register. If bit IA is 0, the contents of the address field of the instruction are loaded into the specified register; if bit IA is 1, the contents of the location specified by the address field are loaded into the specified register.
For single word instruction:
EDISP - - - (1, XRl, XR2, or XR3) For double word instruction with IA = 0:
ADDRESS - - -(1 I XRl, XR2, or XR3) For double word instruction with IA
=
1:(ADDRESS)--- (1 I XRl, XR2 I or XR3) Indicators: Carry and Overflow are not affected.
Affected: (I), (XRl), (XR2) I or (XR3) "
3-3
88A00026A
STX STORE INDEX 2.4p.s
o 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
OP F T 'A COND
1° 1 1 ° 1! 1! -I-! ° ° ° ° ° ° ° I
,x
, II ,
~ ADDRESS, I ,
~, I
, , ,x
o 1 2 3 4 5 6 7 8 9 101112131415 0 1 2 3 4 5 6 7 8 9 101112131415
The Store Index instruction stores the contents of the register specified by the tag (T) field at the effec-tive address. The register is specified as follows:
T Register
00 I
01 XRl
10 XR2
11 XR3
(I, XRl, XR2, or XR3) - - - (EA)
Indicators: Carry and Overflow are not affected.
Affected: (EA)
LD LOAD ACCUMULATOR 2.4p,s
o 1 2 3 4 5 6 7 8 9 1011 12 13 14 15
OP F T 'A COND