SPARC supports three types of traps: precise, deferred, and interrupting. A precise trap (also referred to as a synchronous trap) is induced by a particular instruction and occurs before the processor state is changed by the trap-inducing instruction. All instructions preceding the trap inducing instruction have completed execution.
Deferred traps are caused by a trap-inducing instruction, but the processor state may have been changed by other instructions executing after the trap-inducing instruction. Deferred traps are generated by a unit other than the integer unit executing instructions in parallel with the IU, such as the internal FPU within a RT620 or the CY7C602 FPU in a CY7C601 system.
Interrupting traps occur when an external event interrupts the processor. They are not related to any particu-lar instruction and occur between the execution of instructions. Memory exceptions, RESET, and interrupt requests belong to this group of traps. Interrupting traps are also sometimes referred to as an asynchronous traps.
Several details concerning the handling of exceptions are processor dependent. Detailed information on trap handling is given in Section 3.9 (RT620) and Section 6.5.5 (CY7C601).
2.4.5.1 Precise Traps
Precise traps are caused by the actions of an instruction, with the trap stimulus occurring either internally to the SPARC processor or from an external signal which was provoked by the instruction. These traps are taken immediately and the instruction that caused the trap is aborted before it changes any state in the proces-sor. All instructions in the SPARC pipeline that preceded the trap-inducing instruction complete execution before the trap is recognized.
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Precise traps generated by internal hardware are associated with an instruction. The trap condition is de-tected during the Execute stage of the instruction and the trap is taken immediately, before the instruction can complete.
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illegal instruction trap
An illegal instruction trap occurs:
• when the UNIMP instruction is encountered,
• when an unimplemented instruction is encountered (excluding FPops and CPops),
• in any of the situations below where the continued execution of an instruction would result in an illegal processor state:
1. Writing a value to the PSR's CWP field that is greater than the number of implemented windows (with a WRPSR)
2. Executing an alternate space instruction with its i bit set to 1 3. Executing a RETT instruction with traps enabled (ET=l)
Unimplemented floating-point and unimplemented coprocessor instructions do not generate an illegal in-struction trap. They generate fp exception and cp exception traps, respectively.
privileged instruction
This trap occurs when a privileged instruction is encountered while the PSR's supervisor bit is reset (S=O).
fp disabled
An fp disabled trap is generated when an FPop, FBfcc, or floating-point Load/Store instruction is encoun-tered while the PSR's EF bit =0. In the case of the CY7C601, this trap can also be generated by these instructions if no FPU is present.
cp disabled (CY7C601 only)
A cp disabled trap is generated when a CPop, CBccc, or coprocessor Load/Store instruction is encountered while the PSR's EC bit =0, or if no coprocessor is present (CP input signal =1).
window overflow
This trap occurs when the continued execution of a SAVE instruction would cause the CWP to point to a window marked invalid in the WIM register.
window underflow
This trap occurs when the continued execution of a RESTORE instruction would cause the CWP to point to a window marked invalid in the WIM register. The window underflow trap type can also be set in the PSR during a RETT instruction, but the trap taken is a reset. Refer to Chapter 12 for the instruction definition forRETT.
memory address not aligned
Memory address not aligned trap occurs when a load or store instruction generates a memory address that is not properly aligned for the data type or if a JMPL instruction generates a PC value that is not word aligned (low-order two bits nonzero).
tag overflow
This trap occurs if execution of a TADDccTV or TSUBccTV instruction causes the overflow bit of the inte-ger condition codes to be set. Refer to the instruction definitions of TADDccTV and TSUBccTV in Chapter 12, SPARC Instruction Set for details.
trap instruction
This trap occurs when a Ticc instruction is executed and the trap conditions are met. There are 128 program-mable trap types available within the trap instruction trap (see Chapter 12, Ticc Instruction).
2.4.5.2 Deferred Traps
Deferred traps differ from precise traps in that the trap-inducing instruction may be followed by other instructions that may change the state of the processor. For ROSS SPARC, deferred traps may be caused by a trap-inducing FP or CP operation. Note that FP and CP register loads and stores are considered a type of load and store instruction, and therefore are not a deferred trap.
The servicing of a deferred trap is facilitated by the use of a deferred-trap queue. This queue contains the trap-inducing instruction and its address, as well as other FP (and/or CP, in the case ofthe CY7C60 1) instruc-tions that may have been fetched. This allows the deferred-trap handling routine to recover from the deferred trap by emulation or re-execution of the trap-inducing instruction. The topics of floating-point queues are covered in Section 3.5.1.1 for the RT620 and Section 7.3.1.2 for the CY7C602 FPU. The topic of floating-point traps for the RT620 is further addressed in Section 3.9.8.
2.4.5.3 Interrupting Traps
Interrupting traps occur in response to the interrupt level inputs, memory exceptions, or reset. They differ from both precise traps and deferred traps in that they are not necessarily caused by a particular instruction, or may be due to an exception caused by a previous instruciton. Interrupting traps also differ from the other trap types in that they are not required to provide a means of emulating an instruction (such as the FP queue) that caused an interrupting trap.
2.4.5.3.1 Interrupt Requests
Interrupt requests are made to the SPARC processor by means of a group of interrupt level signals (MIRL(3:0) for the RT620 and IRL(3:0) forthe CY7C601). The interrupt level on these lines are compared against the four-bit processor interrupt level (PIL) field in the processor state register (PSR) of the integer unit. If the interrupt level is greater than the setting of the PIL, an interrupting trap is taken by the processor.
Note that (M)IRL(3:0) = '0000' denotes no interrupt request and' 1111' denotes a non-maskable interrupt request.
For processor-specific information on interrupts, refer to Section 3.9.7 for the RT620 or Section 6.5.3 for the CY7C601.
2.4.5.3.2 Reset
The reset trap is a special case of the external asynchronous trap type. It is asynchronous because it is trig-gered by asserting the RESET input signal. Upon recognizing the RESET signal, the RT620 or CY7C601 enters reset mode and stays there until the RESET line is deasserted. After reset, the processor enters Execute mode and then begins the execute trap procedure. The processor modifies the enable traps bit (ET=O), and the supervisor bit (S=l). It then sets the PC to 0 (rather than changing the contents of the TBR), the nPC to 4, and transfers control to location O. All other PSR/ields, and all other registers retain their values/rom the last Execute mode.
If the processor was reset from error mode, then the normal actions of a trap have already been performed, including setting the tt field to reflect the cause of the error mode. Because this field is not changed by the reset trap, a post-mortem can be conducted on what caused the error mode. The processor enters error mode whenever a synchronous trap occurs while traps are disabled.
Note: Upon power-up reset the state of all registers other than the PSR are undefined.
2.4.5.3.3 Memory Exceptions
Memory exceptions are signaled to the processor by the cache controller. In general, these may be due either to a cache access exception or to an MBus exception that is signalled by the responding MBus unit.
Memory exceptions are signalled to the RT620 by the RT625 CMTU using the IMEXC signal. In a similar fashion, the CY7C604/605 CMU uses the MEXC signal to signal memory exceptions to the CY7C601. The IU (either RT620 or CY7 C60 1) This interface and other details concerning memory exceptions are covered in the chapters specific to these processors.
2.4.5.4 Trap Operation
Once a trap is taken, the following operations take place:
• Further traps are disabled (asynchronous traps are ignored; synchronous traps force an error mode).
• The S bit of the PSR is copied into the PS bit; the S bit is then set to 1.
• The CWP is decremented by one (modulo the number of windows) to activate a trap window.
This happens regardless of the contents of the WIM register, which is ignored upon entering a trap.
• The PC and nPC are saved into r[17] and r[18], respectively, of the trap window.
• The tt field of the TBR is set to the appropriate value.
• If the trap is not a reset, the PC is written with the contents of the TBR and the nPC is written with TBR + 4. If the trap is a reset, the PC is set to address zero and the nPC to address four.
The SPARC architecture does not automatically save the PSR into memory during a trap. Instead, it saves the volatile S bit into the PSR itself and the remaining fields are either altered in a reversible manner (ET and CWP), or should not be altered in the trap handler until the PSR has been saved to memory.
2.4.5.4.1 Trap Addressing
The trap base register (TBR) is made up of two fields, the trap base address (TBA) and the trap type (tt).
The TBA contains the most-significant 20 address bits of the trap table, which is in external memory. The trap type field, which was written by the trap, not only uniquely identifies the trap, it also serves as an offset into the trap table when the TBR is written to the PC. The TBR address is the first address of the trap handler.
However, because the trap addresses are only separated by four words (the least-significant four bits ofTBR are zero), the program must jump from the trap table to the actual address of the particular trap handler.
Of the 256 trap types allowed by the 8-bit tt field, half are dedicated to hardware traps (0-127), and half are dedicated to programmer-initiated traps (Ticc). For a Ticc instruction, the processor must calculate the tt
value from the fields given in the instruction, while the hardware traps can be set from a table such as the one below. The tt field remains valid until another trap occurs. Refer to the Ticc instruction definition in Chapter 12 for further information.
2.4.5.4.2 Trap Types and Priority
Each type of trap is assigned a priority. When multiple traps occur, the highest priority trap is taken, and lower priority traps are ignored. In this situation, a lower priority trap must either persist or be repeated in order to be recognized and taken. Refer to Table 3-7 for a trap priority listing for the RT620 or Table 6-7 for a trap priority listing for the CY7C601.
2.4.5.4.3Return From Trap
On returning from a trap with the RETT instruction, the following operations take place:
• The CWP is incremented by one (modulo the number of windows) to re-activate the previous window.
• The return address is calculated.
• Trap conditions are checked. If traps have already been enabled (ET=l), an illegal instruction trap is taken. If traps are still disabled but S=O, or the new CWP points to an invalid window, or the return address is not properly aligned, then an error mode/reset trap is taken.
• If no traps are taken, then traps are re-enabled (ET=l).
• The PC is written with the contents of the nPC, and the nPC is written with the return address.
• The PS bit is copied back into the S bit.
The last two instructions of a trap handler should be a JMPL followed by a RETT. This instruction couple causes a non-delayed control transfer back to the trapped instruction or to the instruction following the trapped instruction, whichever is desired. See the RETT instruction definition for details.
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