II I PROCESSOR STATE REG (PSR) I 1,1
2.1 Programming Model
The SPARC register model, register window mechanism, processor states, supervisor/user modes, control/
status registers, and data types are described in detail in this section. The concepts and properties explained here are central to an understanding of the SPARC operation.
Figure 2-1 represents the SPARC register set available to the programmer. The register sets for the hyper-SPARC RT600 and the CY7C600 families are identical with the following exceptions:
• The instruction cache control register (lCCR) has been added to the RT620 Central Proces-sing Unit (CPU) in order to allow control of the on-chip instruction cache.
• In order to provide a diagnostic interface for chip testing, the diagnostic register (DIAG) has been added to the RT620. This register is for manufacturing test purposes, and is not intended for user access.
• The floating point unit (FPU) portion of the RT620 has a four-entry pre-queue and a three-entry post-queue, as compared to the CY7C602 FPU three-three-entry queue.
• The features of the hyperSPARC RT625 Cache Controller, Memory Management, and Tag Unit (CMTU) have been enhanced over the previous CY7C604 and CY7C605 CMU s. There-fore, control registers such as the system control register (SCR), reset register (RR), synchronous fault status register (SFSR), and the asynchronous fault status register (AFSR) have been changed.
SPARC registers can be divided into two general classifications: working registers and control/status regis-ters. Working registers are those used for data and addressing operations. They are called r-registers for the integer unit (IU), orf-registers in the floating-point unit. The various control/status registers record status or control the state of a processor or memory management unit (MMU).
The 136 r-registers of the integer unit are divided into eight register windows, as described in the next sec-tion. The 32 f-registers of the floating-point unit are a directly addressed register file (referred to as freg O .. /reg 31) and are discussed in section 2.1.3. The various control/status registers for the IU, the FPU, and the cache controller/MMU are discussed in their respective sections.
All registers for SPARC are 32-bits in length, although floating-point double-precision instructions allow an adjacent and aligned floating-point data register pair to be accessed as a single 64-bit register. Also note that while all control registers are 32-bits in length, some of the bit fields may be designated as reserved.
Reserved bits are non-writable, and are returned as zero when the register is read. It is good programming practice to write zeros into a reserved bit field when writing to a control register of this type. This practice avoids upgrade problems with later hardware versions.
2.1.1 Supervisor/User Modes
In support of multitasking, SPARC employs a supervisor/user model of operation. The processor is in super-visor mode when the S bit in the processor state register (PSR) is set, and in user mode when S is reset (see Section 2.2 .1.2). The state of this bit determines whether or not privileged instructions may be used. Privi-leged instructions restrict control register access to supervisor software, preventing user programs from accidentally altering the state of the machine.
A program running in user mode may enter supervisor mode by encountering a software or hardware trap.
A return to user mode is accomplished by executing a return from trap (RETT) instruction, which restores the state of the S bit to what it was before the trap was taken. A commonly used trap return is the JMPL, RETT delayed control transfer couple (refer to Section 2.4.3.4.4). This restores both the PC and nPC (see Section 2.2 .1.1) and the previous state of the S bit.
Previous Wiudow (CWP + 1)
The SPARC architecture uses a "windowed" register file model in which the file is divided up into groups of registers called windows. This windowed register model simplifies compiler design, speeds procedure calls, and efficiently supports AlI programming languages such as Prolog, LISP and Smalltalk.
The 136 r-registers of the RT620 and CY7C60l are 32-bits wide and are divided into a set of 128 window registers and a set of eight global registers. The 128 window registers are grouped into eight sets of 24 r-reg-isters called windows. One of these eight windows is selected by setting the Current Window Pointer (CWP), a 5-bit field in the processor state register (PSR) (see Section 2.2 .1.2). Within each window, the pro-grammer can directly access 24 windowed r-registers by register number (as described in Table 2-1). The eight global registers may be accessed regardless of the window selected by the CWP.
Table 2-1. Register Addressing
Register Alternate Register
Number Register Number Group Name r[24] to r[31] i[O] to i[7] ins
r[16] to r[23] 1[0] to 1[7] locals r[8] to r[15] 0[0] to 0[7] outs r[O] to r[7] g[O] to g[7] globals
The windowed register file is implemented as a circular stack, with the highest numbered window joined to the lowest. For the eight windows implemented in SPARC, window 7 adjoins window O.
Note that each window shares its ins and outs with adjacent windows (refer to Figure 2-2). Outs from a pre-vious window (CWP+ 1) are the ins of the current window, and the outs of the current window are the ins ofthe next window (CWP-1). While only adjacent windows share ins and outs, globals are shared by all windows. A window's locals, on the other hand, are not shared at all, belonging only to that window.
T E e H N O ' 0 G Y,
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===========;;::S;;::P;;::1\=R;;::C=P;;::ro:;;g;:;:r;;::a;;::m;;::m=iD:;;g;:;:;;::E;;::D;;::V;;::ir;;::o;;::D;;::m;;::e;;::D=t An alternative approach to understanding SPARC window registers is to note that the Current Window Pointer (CWP) acts as an index pointer within the stack of 128 window registers. Changing the Current Win-dow Pointer by one offsets the r-register addressing by 16. Since 24 r-registers can be addressed with each CWP value, incrementing or decrementing the CWP results in an eight register overlap in register addres-sing. This overlap of window register addressing creates the in-out feature of the windowed registers.Programming Note:
After power-on reset, the state of the Current Window Pointer and the WlM register (see Section 2.2 .1.3) are undefined. The power-on reset trap routine must initialize the CWP and WIM register for correct opera-tion.
2.1.2.1 Parameter Passing Using Register Windows
Register window overlap provides an efficient means of passing parameters during procedure calls and re-turns. One method of implementing a procedure call that takes advantage of the overlap is to have the calling procedure move the parameters to be passed into its outs registers, then execute a CALL instruction. A SAVE instruction then decrements the CWP to activate the next window. The calling procedure's outs be-come the called procedure's ins, making the passed parameters directly accessible.
When a called procedure is ready to return results to the procedure that called it, those results are moved into its ins registers and it then executes a return, usually with a JMPL instruction. A RESTORE instruction increments the CWP to activate the previous window. The called procedure's ins are still the calling proce-dure's outs; thus the results are available to the calling procedure. Note that the terms ins and outs are defined relative to calling, not returning.
If the calling procedure must pass more parameters than can be accommodated by the outs and globals, the additional parameters must be passed on the memory stack. One method of handling the stack pointer is to dedicate an out register in the current window to hold the stack pointer (see Figure 2-3). After a CALL, this pointer (which is now in an ins register) can be used as the frame pointer for the called procedure. The SAVE instruction, in addition to decrementing the CWP, also performs an ADD using registers from the current window and placing the result in a register in the next window. This feature can be used to set a new stack pointer for the called procedure from the old pointer in the calling procedure. RESTORE also performs an ADD, using registers in the current window and placing the result in the previous window.
2.1.2.2 Window Overflow and Underflow
No matter how many windows a register file has, it is possible that at some point the program will try to use more than are available. Since the register file is a circular stack, something must be done to prevent over-writing the oldest window as the stack wraps around.
Window management is provided by using bits in the window invalid mask (WIM) register to mark win-dows that will trigger an underflow or overflow trap (see Section 2.2 .1.3). If a SAVE instruction points the CWP to a marked window, a window overflow trap is generated. This means that only seven of the eight windows are available for calls, because the last window must be saved for the trap handler. However, since a typical overflow trap handler would transparently save one or more of the oldest windows to memory, the program sees an apparently infinite number of windows.
The CWP is automatically decremented upon encountering a trap. This happens without generating another window overflow trap, regardless of the state of the WIM register. By setting at least one window as masked by the WIM register, the system is assured of at least one window for use by the trap handler.
T E e H N 0 LOG Y,
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Figure 2-3. Registers as Seen by a Procedure
A RESTORE instruction causes a window underflow trap if it attempts to restore to a window invalidated by the WIM register. Execution of a return from trap (RETT) instruction under the same circumstances will also generate an underflow trap. SAVE, RESTORE, and RETT always check the WIM register before com-pleting their actions.
For example, if the procedure using the window 0 executes a CALL and SAVE sequence and the WIM bit 7 is set, a window overflow trap occurs. The overflow trap handler may safely use only the locals of w7, because w7's ins are wO's outs and w7's outs are w6's ins.
Active window = 0
T E e H N 0 L O G ' ,
,$
===========:;;;;S:;;;;P:;;;;1\:;;;;R=C:;;;;P=ro;:;g;;;:r:;;;;3:;;;;ID:;;;;ID=ill;:;g;;;::;;;;E:;;;;ll:;;;;V:;;;;ir:;;;;o:;;;;ll:;;;;ID:;;;;e:;;;;ll=t The overflow trap handler is responsible for saving one or more of the least recently used windows to the memory stack. Simulations of register file management methods show that saving and restoring one window at a time is the simplest and most effective algorithm for handling overflow and underflow. The stack pointer to the window-save area must be aligned to a word boundary in valid memory and, for efficiency, should be doubleword aligned. This is because it is faster to load and store doublewords than to load and store words.A linear sequence of doubleword loads and stores is also used to speed up context switches. In a context switch, only the windows containing valid data are saved, and on average this is about half the number of r-register windows, minus one for the reserved trap window.
2.1.2.2.1 Alternate Register Window Usage
Although the windowing layout is particularly well suited to procedure calls and returns, hardware does not force their use for that purpose alone. Except for the eight-register overlap and the partial fixing of the func-tion of several registers by the instrucfunc-tion set (see Secfunc-tion 2.1.2 .3), register windows can be viewed and manipulated as needed to fit the application at hand.
For example, the register set can be treated as a flat register file. Access to any particular register in any win-dow is obtained by writing its winwin-dow value into the Current Winwin-dow Pointer located in the processor state register. Moreover, windows naturally segment registers into blocks that could be dedicated to specific pur-poses and accessed through the CWP. Register saving and parameter passing could be done with a standard push/pop stack in memory, although this would substantially increase bus traffic.
For real-time and embedded controller systems, where Fast Context switching may be more important than procedure calling, the register file can easily be divided into banks of registers separated by trap handling windows set up by the WIM register (see Section 2.2 .1.3). Switching from one register bank to another is accomplished by writing to the CWP field of the processor state register. Globals are accessible by all pro-cesses.
2.1.2.3 Special Registers
In general, the window registers seen at any given time can be used in any manner desired, while keeping in mind that windows overlap at both ends. However, the instruction set does fix the use of r[O] and partially fixes the use of r[I5].
Global register r[O] always returns the value 0 when read, making the most frequently used constant easily available at all times. In addition, when addressed as a destination operand, r[O] discards the value written to it.
The CALL instruction writes its own address into register r[I5] (out register 7) of the calling procedure's window. If a SAVE instruction then activates a new window, r[I5] of the old window becomes r[3I] (in reg-ister 7) of the new window and serves as the return address to the calling procedure. However, if the regreg-ister is needed for some other purpose, the return address can be saved to a stack or simply overwritten.
Two other registers are also used by hardware to save information during a trap. Registers r[I7] and r[18]
(locals 1 and 2) of the trap window (not the trapping procedure's window) are used to save the contents of the program counters (PC and nPC) at the time the trap is taken. Because the trap window locals are all a trap handler is allowed to use (unless it saves to the system stack), this limits the trap handler's usable regis-ters to six.
T E C H N O L O G Y ,
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64-bit double register pairs. 31
o
31 0freg 0 freg 1
freg2 frea3
frea4 freg5
freg6 freg 7
freg8 freg 9
freg 10 freg 11
freg 12 freg 13
freg 14 freg 15
freg 16 freg 17
freg 18 freg 19
freg 20 freg 21
freg22 freg 23
freg 24 freg25
freg 26 freg 27
freg 28 freg 29
frea 30 frea 31
Figure 2-4. FPU Register File
2.1.3 Floating-Point Register File (FREGS)
In addition to the 132 r-registers, SPARC defines a set of 32-bit floating-point data registers, referred to as J-registers. The RT620 and CY7C602 fp register files each provide a set of 32J-registers. These registers can be accessed as 32 registers containing single precision (32-bit) data types or as 16 pairs of registers con-taining double precision (64-bit) data types. Double precision register pairs are always addressed as adjacent even-odd registers.