hyperSPARC CPU Bus Timing Waveforms

This subsection supplies a sampling of bus timing diagrams related to read, write, atomic read-write, memory exceptions, reset, interrupt, traps, and error mode. These diagrams represent a subset of possible combinations of bus activities.

3.7.3.1 List of Figures: page

Figure 3-17. Instruction Access with Instruction Cache Hit ... 3-37 Figure 3-18. Read Accesses with External Cache Hit ... 3-38 Figure 3-19. Write Accesses with External Cache Hit ... 3-39 Figure 3-20. Atomic Read-Write Accesses with External Cache Hit ... 3-40 Figure 3-21. Write Access Followed by Read Access with External Cache Hit ... 3-41 Figure 3-22. Write Access Followed by Write Access with External Cache Hit ... 3-42 Figure 3-23. Read Access with External Cache Miss ... 3-43 Figure 3-24. Write Access with External Cache Miss ... 3-45 Figure 3-25. Atomic Read-Write Access with External Cache Miss ... 3-47 Figure 3-26. Data Read Access with Memory Exception ... 3-49 Figure 3-27. Instruction Read Access with Memory Exception ... 3-51 Figure 3-28. Reset Timing ... 3-53 Figure 3-29. Interrupt Timing ... 3-56 Figure 3-30. Error Timing ... 3-57

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Figure 3-17. Instruction Access with Instruction Cache Hit*

* This series of read activities corresponds to . . .

four user instruction reads (Fetches) that results in an internal instruction cache hit followed by one user instruction read (Fetch) that results in an external cache hit.

Figure 3-18. Read Accesses with External Cache Hit*

*

This series of read activities corresponds to ...

a user instruction read (Fetch) that results in an external cache hit followed by

a user halfword read (e.g., LDSH or LDUH) that results in an external cache hit followed by a user word read (e.g., i l l or LDP) that results in an external cache hit followed by a user doubleword read (e.g., LDD or LDDP) that results in an external cache hit followed by a user byte read (e.g., LDSB or LDUB) that results in an external cache hit followed by a user instruction read

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Figure 3-19. Write Accesses with External Cache Hit*

*

This series of read/write activities corresponds to ...

a supervisor instruction read (Fetch) that results in an external cache hit followed by a supervisor byte write (e.g., STB) tb,at results in an external cache hit followed by a supervisor instruction read (Fetch) that results in an external cache hit followed by a supervisor word write (e.g., ST or STF) that results in an external cache hit.

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Figure 3-20. Atomic Read-Write Accesses with External Cache Hit*

*

This series of read/write activities corresponds to ...

a user instruction read (Fetch) that results in an external cache hit followed by

a user atomic read/write (e.g., LOSTUB) that results in an external cache hit followed by a user instruction read (Fetch) that results in an external cache hit followed by

a user word read (e.g., LDO or LOOp).

T E C H N O L O G Y ,

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Figure 3-21. Write Access Followed by Read Access with External Cache Hit*

* This series of read activities corresponds to ...

a user instruction read (Fetch) that results in an external cache hit followed by a user halfword write (e.g., STH) that results in an external cache hit followed by a user word read (e.g., LD or LDF) that results in an external cache hit followed by two user instruction reads (Fetches).

T E e H NO LOG Y,

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Figure 3-22. Write Access Followed by Write Access with External Cache Hit*

* This series of read activities corresponds to ...

a user instruction read (Fetch) that results in an external cache hit followed by a user halfword write (e.g., STH) that results in an external cache hit followed by a user byte write (e.g., STB) that results in an external cache hit followed by a user instruction read.

T E e H N 0 LOG Y,

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Figure 3-23. Read Access with External Cache Miss* (page 1 of 2)

* This series ofread activities corresponds to ...

a user instruction read (Fetch) that results in an external cache hit followed by

a user halfword read (e.g., LDSH) that results in an external cache miss and a cache line fill (where the halfword is latched by the processor as soon as it is available) followed by a user word read (e.g., LD or LDF) that results in an external cache hit followed by a user doubleword read (e.g., LDD or LDDF) that results in an external cache hit followed by a user byte read (e.g., LDSB or LDUB) that results in an external cache hit followed by a user instruction read (Fetch)

T E C H N O L O G Y ,

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Figure 3-23. Read Access with External Cache Miss (page 2 of 2)

T E e H N 0 LOG Y,

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Figure 3-24. Write Access with External Cache Miss* (page 1 of 2)

* This series of read/write activities corresponds to ...

a supervisor instruction read (Fetch) that results in an external cache hit followed by

a supervisor byte write (e.g., STB) that results in an external cache miss and a cache line fill followed by a supervisor instruction read (Fetch) that results in an external cache hit followed by

a supervisor word write (e.g., ST or STF) that results in an external cache hit.

T E C H N O L O G Y ,

Figure 3-24. Write Access with External Cache Miss (page 2 of 2)

T E C H N O L O G Y ,

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Figure 3-25. Atomic Read-Write Access with External Cache Miss* (page 1 of 2)

* This series of read/write activities corresponds to ...

a user instruction read (Fetch) that results in an external cache hit followed by

a user atomic read/write (e.g., LDSTUB) that results in an external cache miss and a cache line fill (where the byte is latched by the processor as soon as it is available) followed by

two user instruction reads (Fetches) that result in external cache hits.

T E e H N 0 L 0 0 Y,

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Figure 3-25. Atomic Read-Write Access with External Cache Miss (page 2 of 2)

T E C H N O L O G Y ,

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Dans le document SPARC RISC USER'S GUIDE (Page 131-144)