hyperSPARC CPU Pinouts

IMA<31:18>

MIRL<3:0> IMA<17:15>

PRST IMA<14:3>

IMBNA IMA<2:0>

IMEXC IMD<63:0>

IMDS RT620 IMASI<5:0>

hyperSPARC

IMSIZE<1:0>

PHOLD CPU

IMCLK IMTYPE<1:0>

TCK PNULL

TDI PERROR

TRST TDO

TMS

Figure 3-15. RT620 Signals IMCLK - (input) 1MB Clock

This is the basic clock for all the Intra-Module components. All the Intra-Module signals are driven and sampled on only the rising edge of the IMCLK. The RT620 uses only the IMCLK clock (not the MBus clock). The rising edge ofIMCLK defmes the beginning of each pipeline stage. The processor cycle is equal to a full clock cycle.

IMA < 31:18 > - (output, bi-state) Intra-Module Address Bus IMA < 17:15 > - (output, tri-state) Intra-Module Address Bus IMA < 14:3 > - (input/output, tri-state) Intra-Module Address Bus IMA < 2:0 > - (input/output, bi-state) Intra-Module Address Bus

The 32-bit address bus carries instruction or data address during a fetch or Load/Store operation.

Addresses are sent out unlatched and must be latched external to the RT620. The address on the IMA

< 31:0 > is a virtual address.

IMD < 63:0 > - (input/output, tri-state) Intra-Module Data Bus

These pins form a 64-bit bi-directional data bus that serves as the interface between the CPU and memory.

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Store data is sent out unlatched (and is latched by the RT625). Alignment for load and store instruc-tions is performed by the RT620. Double words are aligned on 8-byte boundaries, words on 4-byte boundaries, and halfwords on 2-byte boundaries.

IMASI < 5:0 > - (output, bi-state) Intra-Module Address Space Identifier

These 6 bits constitute the address space identifier (ASI). The ASI identifies the memory address space to which the instruction or data access is being directed. The IMASI bits are sent out unlatched simultaneously with the address (and are latched by the RT625).

The following table describes IMASI generation:

Bus Activity IMASI

instruction fetch 001000 (binary) + supervisor bit Load/Store access 001010 (binary) + supervisor bit Load/Store alternate ASI immediate field

IMSIZE < 1:0 > - (output, bi-state) Intra-Module Access SIZE

These two pins indicate the SIZE of the current access. Instruction accesses are always doubleword size. Because the data bus is 64-bits wide, doubleword accesses can be performed in a single access.

The value of the size bits during a given cycle relates only to the address which appears on pins IMA<31 :0>. The IMSIZE<1 :0> bits are sent out unlatched (and are latched by the RT625). Size val-ues are defined as follows:

Bus Activity instruction fetch Load/Store double Load/Store word Load/Store haIfword Load/Store byte

IMTYPE < 1:0> - Intra-Module Access TYPE

• IMTYPE < 1 > - (output, bi-state)

• IMTYPE < 0 > - (output, tri-state)

SIZE < 1:0 >

11 (binary) 11 (binary) 10 (binary) 01 (binary) 00 (binary)

These two pins indicate the current access TYPE. Instruction accesses are always type read. The val-ue ofthe type bits during a given cycle relates only to the address which appears on pins IMA<31 :0>.

The IMTYPE bits are sent out unlatched (and are latched by the RT625). Type values are defined as follows.

IMTYPE< 1 > IMTYPE<O> Meaning

0 0 N ormaI write (store)

0 1 Normal read (load or instruction fetch)

I 0 Locked write (atomic store)

I I Locked read (atomic load)

PHOLD - (input) processor HOLD

This signal is used by the CMTU to hold the processor and prevent pipeline advancement. When the PHOLD input signal is asserted, all pipelines in the RT620 are frozen.

IMDS - (input) Intra-Module Data Strobe

This signal is generated by the CMTU to strobe the data into the CPU whenever the valid data is available while the processor is being held. The data strobe is valid only ifPHOLD is asserted during the cycle that precedes the IMDS occurrence.

IMEXC - (input) Intra-Module Exception

This signal is generated by the CMTU to indicate an exception condition to the CPU.

IMBNA - (input) Intra-Module Bus Not Available

This signal is generated by the CMTU to indicate that the CMTU is using the Intra-module Bus. This feature allows data in a missed cache line to be filled as a background task while the processor contin-ues executing instructions from the on-chip instruction cache. The processor can resume instruction execution once the CMTU has provided the data which caused the processor hold.

PNULL - (output, bi-state) Processor Nullify

The RT620 asserts PNULL to indicate that the current external cache access is being nullified. As-serting PNULL nullifies the access already latched by the external cache subsystem.

PNULL is generated under the following conditions:

1. An on-chip instruction cache hit occurred.

2. An on-chip instruction cache miss occurred and a Fast Branch was not taken.

3. An exception is pending.

4. No instruction fetch is pending and no load or store instruction is pending.

PERROR - (output, bi-state) Processor ERROR

This pin is asserted when the processor is in the ERROR mode, which occurs when a synchronous trap is encountered while traps are disabled (i.e., the PSR's ET bit = 0). The only way to restart a processor which is in the error mode state is to trigger a reset by asserting the PRST signal.

PRST - (input) Processor Reset

Assertion of this pin will reset the RT620. PRST must be asserted for a minimum of eight processor clock cycles. After PRST is de-asserted, the processor starts fetching from virtual address O. PRST is latched by the RT620 before it is used.

MIRL < 3:0 > - (input, asynchronous) MBus Interrupt Request Levels

MIRL<3 :0> indicate the interrupt request level. If traps are enabled, this value is compared against the PSR processor interrupt level field to determine if the interrupt should be acknowledged.

MlRL<3:0> are synchronized by the RT620 for two clocks.

The state of these four pins defines the external interrupt level. MIRL < 3:0 >

=

0000 indicates that no external interrupts are pending and is the normal state of the MIRL pins. MIRL < 3:0 > = 1111 signifies a non-maskable interrupt.

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This is a test access port (TAP) clock signal that is independent of the IMCLK. The changes on TAP input signals (TMS and TDI) are clocked into the TAP controller, instruction register, or selected test data register on the rising edge of TCK. Changes at the TAP output signal (TDO) also occur on the rising edge of TCK.

TDI - Test Data Input.

TDI is a TAP input that is clocked into the selected register (instruction or data) on a rising edge of TCK. The TD I input has a built-in pull-up resistor which ensures that an un -terminated or open input is seen by the test logic as a "1."

TDO - Test Data Output.

TDO is a TAP serial data output. The contents of the selected register (instruction or data) are shifted out ofTDO on the falling edge ofTCK. TDO is set to high-impedance except when scanning of data is in progress.

TMS - Test Mode Select.

This control input is clocked into the TAP controller on the rising edge of TCK. The TMS input has a built-in pull-up resistor which ensures that an un-terminated or open input is seen by the test logic as a'1.'

TRST - Test Reset.

TRST initializes the state of the instruction register bits and the TAP controller state machine.

3.7.2 Intra-Module Bus (1MB)

The 1MB is a high-speed 64-bit synchronous processor bus specifically designed for interface with the hy-perSPARC external cache (refer to Figure 3-16). The hyhy-perSPARC external cache (referred to as the e-Cache) is comprised of two or four RT627 CDU s controlled by one RT625 CMTU The 1MB is a synchro-nous data bus designed to transfer one 64-bit data word upon every processor clock (IMCLK) cycle. All data and control signals are sampled on the rising IMCLK edge.

During normal operation, the RT620 asserts IMA<31 :0>, IMASl<5 :0>, IMSIZE<l :0>, and IMTYPE<1 :0>

for all instruction fetches, regardless of whether the instruction cache is enabled. If the instruction is found in the ICACHE, the instruction request is nullified by the RT620 by asserting the PNULL signal. This causes the RT625 to deassert the cache read output enable (CROE) signal, which disables the outputs of the cache RAM. PNULL remains asserted as long as the RT620 ICACHE contains the required instructions. If the ICACHE misses on an instruction request, PNULL is released and the RT625 asserts CROE. Asserting CROE allows the e-Cache to respond to the address supplied by the RT620.

If the RT625 determines that the address supplied on the 1MB is not in the e-Cache, the RT625 asserts the signal PHOLD, which freezes the RT620 processor pipeline. An example of this is illustrated in the timing diagram Figure 3-23 on page 3-43. In addition to PHOLD, the RT625 asserts the IMBNA signal in order to force the RT620 to release the 1MB address and data buses, and the IMTYPE<O> signal. This allows the RT625 to drive the 1MB to transfer data into the RT627 Cache Data Unit. PHOLD is held until the RT625 has fetched the data originally requested by the RT620.

Upon assertion of the IMBNA signal, the RT620 tri-states IMA<17:0>, IMD<63:0>, and IMTYPE<O>.

These signals are directly connected to the RT627 CDUs, and therefore must be tri-stated in order for the

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RT625 to transfer data. IMA<31:18> and IMTYPE<I> are direct inputs to the RT625, and remain driven when IMBNA is asserted.

The hyperSPARC supports data forwarding during cache line fetches. If the RT620 is stopped with PHOLD due to a Cache read miss, PHOLD is released when the requested data is placed on the 1MB by the RT625.

In addition, the IMDS data strobe is asserted for the clock edge upon which the missed data is valid on the 1MB. This allows the RT620 to latch the data on the 1MB as it is transferred to the RT627 CDU s. The IMBNA signal remains asserted by the RT625 until the entire cache line is transferred to the cache.

Memory exceptions are signaled by a one-clock assertion of the IMEXC by the RT625. This is illustrated in Figure 3-27 on page 3-51. The RT620 responds by asserting the PNULL signal, thereby nullifying the instruction or data requests following the memory exception. The RT620 enters a trap routine and begins fetching trap instructions after flushing the pipeline.

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IMA<16:3>

I

IMA<I:7>1 lIMA<I:7>

I

IMA<16:3>

I

IMD<31:0> IMD<63:32> MIRL<3:0>

I

IMA<31:0>

MCLK~

lMA<I:7>

I I

IMD<31:0> IMD<63:32>

I IIMA<1:7>

Figure 3-16. hyperSPARC CPU with 256-Kbyte Cache

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