RT620 hyperSPARC CPU

The RT620 is divided into several different functional blocks: the integer data path (!DP), the floating-point data path (FPDP), the instruction fetch (IFETCH) unit, an on-chip (execute-only) instruction cache, the Instruction Scheduler (ISCHED), the floating-point instruction decode-schedule-and-dispatch controller (FPSCHED), and the Intra-Module Bus Interface Unit (IBIU). These blocks are illustrated in Figure 3-1.

Instructions are fetched for the RT620 by the instruction fetch (IFETCH) block under the control of the inte-ger unit. In order to minimize delays due to instruction cache misses, instructions are simultaneously requested from the instruction cache and the IBIU. Instructions are supplied to the IFETCH by the instruc-tion cache if a cache hit occurs, or from external memory through the IBIU in the case of a cache miss. The IBIU instruction fetch request from external cache is nullified if an internal instruction cache hit occurs.

T E C H N O L O G Y ,

INSTRUCTION FETCH

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INTIiGER REGISTI,R (IREGS)

GLOBAL DECODER.

DEPENDENCY CHECKER.

SCHEDULER, & CONTROL (ISCHED)

EXCEPTION LOGIC

ISCHED Instruction_Address

Instruction

Data Address

INSTRUCTION CACHE (ICACHE)

FLOATING POINT REGISTERS (FREGS)

IMBBUS INTERFACE

UNIT (IBIU)

Control Address

Figure 3-1. RT620 hyperSPARC CPU Block Diagram

FPDP

Once an instruction pair is fetched, it is globally decoded by the ISCHED block, The instruction pair is scheduled for multiple or single instruction launch depending upon the instruction combination and the execution resources required. If an instruction pair (also called an instruction packet) cannot be executed together, the packet is split and the individual instructions are executed singly and in order. Floating-point instructions are dispatched to the floating-point unit by the ISCHED, where they are locally decoded by the FPSCHED unit. Local decoding of the integer instructions is performed by a sub-block of the integer data path (IDP). Figure 3-1 illustrates the functional blocks of the RT620.

IDP - The integer data path is comprised of several units. The arithmetic and logic unit (ALU) handles integer arithmetic, logical, and shift instructions. The load and store unit (LSU) handles instructions that load and store data between memory and registers. This includes the loading and storing of both

T E e H N 0 LOG Y.

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integer and floating-point (fp) data. The program counter unit (PCU) maintains the program counter and performs condition code evaluation. The special register unit (SRU) handles instructions which read and write the SPARC special registers (SREGS). The integer register file (IREGS) is also con-tained in the integer unit data path.

FPDP - The floating-point unit is comprised of the floating-point queue (FPQ), the floating-point arithme-tic unit (FAU), the Floating-Point Multiplier Unit (FMU), the floating-point register file (FREGS), and the floating-point status register (FSR). The FPDP handles all SPARC fp data operations. Note that fp load and store operations, which are considered a subset of standard load and store instructions, are handled by the integer unit. The FPDP generates results which are fully compatible with the ANSI!

IEEE 754-1985 standard.

ISCHED - The Instruction Scheduler performs several key control functions. It provides global instruc-tion decoding, identifying which execuinstruc-tion unit resources are required and determining whether sequential or simultaneous execution is possible. It determines whether data forwarding can be per-formed and whether instruction dispatches (also called "launches") need to be delayed due to data dependencies. It initiates instruction launch and it identifies and controls interrupt and trap handling.

FPSCHED - The point instruction scheduler performs key control functions for the floating-point unit. When the integer unit detects fp instructions in the Decode stage, it off-loads these instructions to the fp functional units and continues processing. Therefore, functional blocks exist which perform necessary decode, scheduling and control for fp operations. The FPSCHED provides floating-point instruction queue control (FPQc), performs fp instruction decoding, and performs fp data dependency and data forwarding resolution. It provides the integer unit with signals that indicate when fp load or store instructions should be delayed due to data dependence on instructions in the FPQ.

It also initiates fp instruction launch.

IFETCH - The instruction fetch unit consists of two major functional blocks: the program counter unit (PCU) and.the instruction fetch controller (IFETCHC).

The program counter unit (PCU) calculates the address of the next instruction to be fetched. It handles instructions which cause program control transfer such as CALL and Branch. This unit handles both integer and fp Branch instructions.

The hyperSPARC CPU fetches two instructions (a packet) at a time. The instructions within the packets are referred to as slots. The first instruction in the packet is referred to as slot-a and the second instruc-tion in the packet is referred to as slot-b. In each clock cycle, the CPU attempts to launch both the instructions in the packet. If the instruction packet cannot be launched together, the instructions are launched singly and in order.

In order to fully support the instruction fetch and launch mechanism, the CPU's on-chip instruction cache supports non-aligned packet boundary accesses. The instruction cache also interfaces with the 64-bit data path of the IBIU block and the external cache subsystem.

ICA CHE - The on-chip instruction cache stores 8 Kbytes of instructions (corresponding to 2048 instruc-tions ).lts inclusion follows the Harvard architectural approach, reducing contention for the bus during memory accesses. This approach allows parallel access to instructions and data. While instructions are fetched from the on-chip ICACHE, the external bus can simultaneously access data from memory.

T E e H N 0 LOG Y,

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When a conflict over bus usage between a data and instruction access does arise (e.g., in the case where an instruction cache miss occurs), the data access receives priority over the instruction access.

When an on-chip instruction cache miss occurs, only one extra clock cycle is required to fetch the in-struction from the external cache. This is accomplished by simultaneously accessing the on-chip instruction cache and the external cache subsystem. If an on-chip instruction cache hit does occur while the external access is in progress, the external access is canceled.

IBIU - The IBIU provides the interface between the CPU and the other hyperSPARC chips. The IBIU samples incoming control signals and propagates controls to appropriate functional blocks. The IBIU is responsible for generating memory access control signals to the cache memory subsystem (e.g., ad-dress, size of data, access-type, etc.). Data and instructions are read from memory, and data is written to memory, through the IBIU.