Maximum Voltage: +0.4 V Minimum Voltage: -0.5 V Maximum Voltage:
+
5.0 V Minimum Voltage: +3.0 V 3.3 METHODS OF DATA TRANSFER08-12!18
There are three methods of accomplishing input/output data transfers: Programmed I/O Transfers. Interrupt Trans-fers. and Data Break TransTrans-fers.
3.3.1 Programmed I/O Transfer
The simplest method of accomplishing an input/output transfer is to employ the Programmed I/O Transfer. This method relies upon the processor to check the Status Flag and service the flag with a subroutine.
3.3.2 Interrupt Facility
A more efficient method of input/output transfers is to employ the Interrupt System. This method uses the Program-med I/O Transfer. but the device signals the processor when a transfer is requied by grounding an INTERRUPT REQUEST line. The processor responds at the end of the current instruction by entering a service routine.
REGULATOR BOARD SLOT
POWER CONTROL
FUSE
CORE MEMORY
SLOTS
Figure 3-3 SA Chassis (H9300)
CABLE TO CONNECT LIMITED FUNCTION
PANEL
7367-3
break at the end of the current cycle. In general. data break requires more hardware than Programmed 1/0. Addi -tional logic is necessary to handle addressing, etc., and some Programmed 1/0 is necessary to initialize and check the status of the device.
3.3.4 The External Bus
The External Bus, which is mechanically and electrically organized the same as the 1/0 Bus on the PDP-S/l or the PDP-S/I computers, plugs into the Omnibus by way of the Positive 1/0 Bus Interface and the Data Break Interface. Each of these modules receives the same signal on the same pins as any other module plugged into the Omnibus. The interfacing details of the External Bus are given in Paragraph 3.1.9 and Volume II of the PDP-BIE Maintenance Manual (DEC-SE-HMM2A-D-D).
The PDP-BIA Miniprocessor Handbook contains the information required to select the type of interface required for the user's device and describes each of the transfer methods in detail.
3.4 MODULE CONFIGURATION ON THE OMNIBUS
The basic PDP-S/A system is comprised of one Central Processor Unit and at least one memory module. Other modules may be plugged into the Omnibus to add additional memory, options, or device interfaces to the system. Table 3-1 lists
For options that require additional modules to hold all the logic, two or more modules may be connected with H851 top connectors (Figure 3-4).
Table 3-1
Slot Assignments for Modules on the Omnibus
Option Option Type of Number o. Omnibus Slot
Designation Module Modules Assignment
Optical Mark Card Reader Control CM8-F Quad 4-last*
Card Reader Control CR8-F Quad 4-last
Interprocessor Buffer DB8-EA Quad 2-last
I/O Option Module DKC8-AA Hex 2-3
Synchronous Modem Interface DP8-EA, EB Quad 2 2-last
Buffered Digital I/O DR8-EA Quad 1 2-last
Positive I/O Interface KA8-E Quad 1 4-last
Programmer's Console KC8-AA, AB PNL.MT. 0 N.A.
Data Break Interface KD8-E Quad 4-last
Redundancy Check Option KG8-EA Quad 4-last
Central Processor Unit KK8-A Hex 1 1
Central Processor Unit
l ~
Quad 2 ReferTiming Generator KK8-E Quad to
Bus Loads Quad Table 2-2
Asynchronous Data Interface KL8-JA Quad 2-last
KL8-M Quad 2-last
Extended Option Module KM8-A Hex 2-3
Line Printer Control LE8-XX Quad 2-last
Line Printer Control LS8-F Quad 1 2-last
Core Memory (8K) MM8-AA Hex 2 4-8
Core Memory (16K) MM8-AB Hex 2 4-8
Read Only Memory (1 K) MR8-AA Quad 2-last
Read Only Memory (2K) MR8-AB Quad 2-last
Read Only Memory (4K) MR8-AD Quad 2-last
Reprogrammable Read Only Memory MR8-FB Quad 2-last
ReadlWrite Memory (1 K) MS8-AA Quad 4-last
ReadlWrite Memory (2K) MS8-AB Quad 4-last
ReadlWrite Memory MS8-AD Quad 4-last
Reader Punch Control PC8-E, PR8-E Quad 4-last
RK05 Disk Control RK8-EA Quad 3 4-last
TU60 Cassette Interface TA8-AA Quad 1 2-last
TU10 DEC Magtape Control TM8-EA, -FA Quad 4 4-last
Point Plot Display Control VC8-E Quad 2 2-last
Video Display and Terminal Control VT8-E Quad 3 4-last
DK8-EP Real Time Clock DK8-EP Quad 2 2-last
AD8-A A/D Converter AD8-A Quad 2-last
*' Last' applies except when considering both a non-expanded 8A600 or 8A620, and the added chassis of an expanded 8A600 or 8A620 (refer to Table 2-2).
3.5 OMNIBUS PIN ASSIGNMENT
Figure 3-5 relates the PDP-8/A modules (both quad and hex) and the Omnibus signals. The connectors are illustrated in the lower part of the figure. The component side of the module is side 1. Individual pins are specified in this manner: B H 1 means connector B, pin H, side 1; DM2 means connector 0, pin M, side 2, and so on. Each connector pin has a corresponding pin on the Omnibus that carries a specific PDP-8/A signal. The upper part of Figure 3-5 relates the signal
Figure 3-4 Modules Connected With HS51 Type Connector
The Omnibus is wired so that the signal appearing on a specific pin is the same for most slots on the Omnibus. For example, pin CK 1 of every Omnibus slot carries signal BUS STROBE L. There are some exceptions and these are noted in Figure 3-5. In slot 1, which has the KKS-A CPU plugged into it. pins AA 1 and CA 1 are tied to
+
5 Vdc instead of being test points as indicated in Figure 3-5. These pins supply the extra+
5 Vdc current required for the MS31 5 module. Slots 2 and 3 also have pins with signals but they are different from the signals in the other slots.1 . BA 1 of slots 2 and 3 carries BA TIERY EM PTY L 2. BB 1 of slots 2 and 3 carries AC LOW L
3. DA 1 of slots 2 and 3 carries PAN EL LOCK L
tes
This pin is connected to ground an the bus but serves as a logic signal within LOW to the aptian modules.
DA 1 of slots 2 and 3 supplies PANEL LOCK to the option modules.
L - - J