The detailed description of the central processor unit (CPU) relies on logic drawings extracted from the complete set of drawings and schematics that appear in Appendix H. The extracted drawings are functional and often comprise logic from more than one sheet of the complete set. Generally, the extracts do not include integrated circuit pin numbers; these can be found in the print set. Appendix H also contains flow diagrams that relate to the significant CPU operations. Become familiar with these flow diagrams; they not only describe the overall CPU operation concisely, but also help you under-stand difficult areas in the detailed logic descriptions.
The CPU manipulates data in response to a predetemined sequence of instructions. In the PDP-8/A both the data and the instructions are stored in memory. An instruction is brought from memory to the processor where it is de-coded to determine, first. what to do to the data, and second, what data is affected. When the data has been manip-ulated, the result is stored within the processor, transferred to a memory location. or transferred to some peripheral equipment.
The CPU logic is contained on a hex-size printed circuit board that plugs into the Omnibus and is assigned the mod-ule designation M8315. Because the Omnibus accepts only four printed circuit board connectors. two of the con-nectors (E and F) extend off the Omnibus. The fingers on these concon-nectors are test points that provide access to certain significant signals in the Instruction Decoder and in the Timing Generator. These test points are shown in the logic drawings (CS M8315-0-1) in Appendix H of this manual.
Figure 4-1 is a block diagram of the CPU. The Programmer's Console. although not physically part of the CPU. is functionally inseparable. The operator can communicate with the major registers and cause data transfers to occur by operating various console buttons. Data is transferred between the console and the processor on the DATA lines in response to control signals generated within the console logic. The console is provided at the customer's option; a Limited Function Panel (not illustrated in the block diagram) is provided with each PDP-8/A. This panel enables an operator to turn power on. to lock out most of the Programmer's Console functions (if the console is part of the sys-tem). and to initiate memory and processor timing. provided certain options are plugged into the Omnibus.
The basic timing cycle of the PDP-8/A is 1.5 J.lS and is divided into four time states. The Timing Generator (TG). be-sides determining the basic timing cycle. provides the synchronizing signals that enable specific CPU operations to occur during assigned time states. These synchronizing signals are applied to all CPU functional sections as well as to memory and to opti'ons and peripherals.
To perform all the operations involved in retrieving, storing, and modifying information. the CPU utilizes the major registers. Data is transferred between registers, between registers and memory (via the Omnibus M D lines). between
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The signals that control the major registers and their gating are developed within the ID largely in response to three variables:
1. Basic instructions (as decoded by the Instruction Register logic)
2. Processor major states (as determined by the Major State Register logic) 3. Time states and time pulses.
These variables are combined in a number of Read-Only Memories (ROMs) to produce control signals that make the major register gating network function.
4.2 TIMING GENERATOR
The various PDP-8/A operations take place in designated time periods of the operating cycle. These time periods are delimited by signals produced in the Timing Generator. located on the CPU printed circuit card. Signals TS 1 through TS4 divide the timing cycle into four nearly-equal states. while signals TP1 through TP4 identify the end of each time state; these two groups of Signals form the foundation for all control signals used in the CPU and in memory.
Figure 4-2 is a block diagram of the Timing Generator. Central to the generator is the Timing Register logic that pro-vides gating Signals for both the CPU Timing logic and the Memory Timing logic; Basic inputs to the Timing Register logic are supplied by a crystal-co.ntrolled clock and by initializing logic that operates when power is applied to the CPU and when the user initiates timing. Normal operation of the Timing Register logic can be modified by either the Memory Stall logic or the 110 Transfer Stall logic. The former suspends timing to accommodate memory that has a slower-than-normal cycle time; the latter suspends timing to facilitate multiple 1/0 transfers between the CPU and a peripheral.
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4.2.1 Power On/Run Logic
The Power On/Run logic is shown in Figure 4-3. The CLEAR L signal and the GO(1) signal are generated in this' logic and are used to begin the timing register operation. The RUN L signal is also produced and is used by the front panel to indicate that timing cycles are being generated. Included in this logic is the auto-start circuit that enables a user to have a program begin automatically at a pre-selected address.
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Figure 4-3 Power ON/RUN Logic
When the power is turned on, POWER OK H (a logic signal generated in the dc power supplies) remains low until the dc voltages have attained a predetermined value. Throughout the time that POWER OK H is low. the CLEAR L signal is asserted. Also, during this time, the de voltages, while not yet at the predetermined value, are of sufficient magnitude to allow the logic to operate. Consequently, the ON L signal is generated, holding the RUN flip-flop in the clear state. When POWER OK H is asserted, the ON DLY one-shot multivibrator is triggered (CLEAR L is negated approximately 30 JiS later because of the delay circuit that includes NOR gate E36; this delay has greater signifi-cance when POWER OK H is negated for some reason, as will be shown later in this section). The ON L signal re-mains low 100 ms, long enough for all memory circuits to stabilize before operations are attempted.
When the ON L signal is negated, the RUN flip·-flop can be set if MEM START L is asserted. MEM START L can be asserted automatically or manually, depending on the user's wish. For the moment assume that the auto-start
fea-The MEM START L signal can be asserted automatically soon after ON L is generated. fea-The CLEAR L signal holds both E42 flip-flops in the clear state when power is applied. If the OFF contact of switch S 1 is open. as shown in Figure 4-3. the MEM START L line is grounded (the Timing Generator is always in time state one - TSL L is as-serted - when not running). Thus. as soon as ON L is negated. the RUN flip-flop is set by the MEM START L signal.
The nature of the RUN flip-flop (DEC74S74) is such that when the clear and preset inputs are low at the same time.
both the 1 and 0 outputs are high. When one of the inputs goes high. the other input then prevails. Thus. when ON L goes high. MEM START L sets the RUN flip-flop.
The auto-start feature is selected by the user with switch S 1. a two-position switch with individually movable con-tacts. If the OFF contact is open. the auto-start feature is enabled; when this contact is closed (in the ON position).
the resulting ground prevents automatic assertion of MEM START L. When auto-start is selected. the program be-gins automatically at the address specified by one of the top five contacts (Figure 4-3). Thus. if contact 4K is closed.
the program will begin at address 4000(8); if contact 400 is closed. the program starts at address 0400(8) (al-though all five contacts may be left open. causing the program to start at address 0000(8). only one of the contacts may be closed at any time). If contact F7 is open. the address selected will be in instruction and data field 0; if F7 is closed. the address is in instruction and data field 7. When there is no memory extension control on the Omnibus.
field 0 is selected regardless of the setting of contact F7. Refer to Paragraph 4.6.4. which describes the sequence of operation for the auto-start feature.
The Timing Generator can be halted by a program instruction. by various front. panel operations. or by negation of the POWER OK H signal. All of these occurrences cause the STOP L signal to be asserted; the next TP3 H pulse clears the RUN flip-flop. and TP4 H then enables a clock pulse to clear the GO flip-flop. The timing halts at the be-ginning of TS 1 L.
When POWER OK H goes low. because power is turned off or because a dc voltage drops below a desired level. a delay circuit prevents the CLEAR L signal from immediately clearing the GO( 1) flip-flop. and. thereby halts timing pre-maturely (premature timing halt is undesirable because of the likelihood of altering the contents of core memory). In-stead. the delay of approximately 30 IJ,S ensures that the RUN and GO flip-flops are cleared at TP3 time and TP4 time. respectively; thus. timing proceeds to its normal conclusion.
4.2.2 Timing Register Logic
The Timing Register logic is shown in Figure 4. The register comprises four DEC74S 194 integrated circuits - 4-bit. bi-directional. shift registers. The four registers are shown in the configuration that applies during normal oper-ation. i.e .. when neither of the stall networks is active.
The diagram in Figure 4-5 will help you visualize the process used to generate the timing signals. Conditions at time to of this diagram can be characterized thusly: Power has been applied to the CPU; the 20 Mhz clock is producing clock pulses; the dc voltages have attained a level sufficient to assert the POWER OK H signal; timing has not yet been started by the user (M EM START L is high). Under these conditions the outputs of registers E9 and E 16 are low. the outputs of E 11. except R2( 1). are low. and the outputs of E 12 may be low or high. depending on the state of flip-flop E8 at power-on.
When the user causes M EM START L to be asserted. the GO flip-flop in the Power On/Run logic is set. asserting the GO( 1) signal. Registers E9 and E 11 are placed in the right shift mode. Each clock pulse shifts a low into R3( 1) of E 11. while shifting-down the high that began in R2( 1). When the high is shifted into E9-R1 (1). the STP (Set Time Pulse) signal places register E 16 in the right shift mode. The next clock pulse causes E 16-R3( 1) (TO) to assume a state opposite to that exhibited by E 16-R2( 1) (T1) before the clock pulse. Simultaneously. the CTS signal places E9 and E 11 in the parallel load mode. The new state of TO is then loaded into E 11. E 11 and E9 revert to the right shift
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