BYTE I/O BUS

The following paragraphs describe the I/O data and control lines of the byte I/O bus. Unless noted, descriptions apply to both internal and external buses.

4.2.1 Input Data Lines

Input data lines lDOO/through ID07/ are terminated on the CPU input bus by lK pullups to +SV. The lines are driven by 7438 TTL power gates, or equivalent, with uncommitted collectors on each controller. When a gate

switches on, the connected line swings to ground potential and places a logical 1 on the B bus. When the gate is switched off, the line swings to +SV. The input data lines are handled the same whether the device controller is located in the mainframe or in an external chassis.

4.2.2 Output Data Lines

Output data lines ODOO/through OD07/ originate at the processor Output Data Register. Data or address information to be transferred over the output data lines is transferred from the A Register, the B Register, or Memory, into the Output Data Register and onto the lines. Lines ODOO/through OD07/ are present at all CPU I/O backplane connectors.

To preserve the expansion capability 6f the byte I/O bus, each device control-ler on the bus is restricted to a single unit load (one TTL gate, 1.6 ma

maximum) on each of the output data lines. Two loads are allowed if one load is a low power TTL gate such as a 74L04.

Output Data Register Binary 1

Binary 0 4.2.3 Input Control Lines

The input control lines on the byte I/O bus are:

• ECIO/ - Concurrent I/O request

• IRPY/ - I/O Reply (spare)

• EINT/ - External interrupt

4-1

ODOX/

OV

+4V nominal

::::

1-"

n Ii

o

~ (1)

-

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c:: en

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(1) en

r-J\~v---~--~+5V

9312 MUX

1Kn +5

RECOMMENDED CONFIGURATION N ";;TEN GATES . M";;FIFTEEN GATES

DEVICE CONTROLLER

~ ^.... N __________ +-+--<l ^OUTPUT

BUS

7438

7438 M

DATA ENABLE

1---

^DATA

I - - - E N A B L E

~---~---~--DATA

~---~---ENABLE

TRANSMITTERS

INPUT BUS

These lines are present in thelIa card connectors in the backplane. The lines are driven by 7438 TTL power gates (or equivalent) with uncommitted collectors in each controller. A lK pullup resistor for each. line is included in the processor, except for EINT/ which has a 470 ohm pullup.

All lines are active (indicate assertion) when they are at ground potential.

For example. ground potential on the EINT/ line causes an external interrupt request.

4.2.4 Output Control Lines

The output control lines on the byte I/O bus are:

•

^IOlX/

•

^I02X/

•

^I03X/

•

^CPRl

•

^CPR2

•

^MRST/

•

^PRIN/

•

^PROT/

•

^SELl

•

^SELO

I/O control bits 1 - 3 from I/O Control Register

Processor Clock

Processor Clock (inverted & delayed 33 nsec from CPRl)

Master Reset Priority In Priority Out Select In Select Out

4.2.4.1 Control Lines IOlX/ through I03X/

These lines are tied to the buffered inverted outputs of the I/O Control Register in the CPU which is set and reset at the microcommand level. Device controllers connected to the I/O bus decode these lines into eight assigned states, indicating various I/O control modes. Table 4-1 provides standard definitions of the eight control flip-flop states. Other definitions can be devised for systems not using standard Microdata firmware and I/O controllers.

Subsequent discussions refer to the conditions of IOlX/ through I03X/ by the logic terms assigned to the eight states of these lines (COXX/, DOXX/.

etc) which are decoded in the I/O controllers.

4-3

Table 4-1. I/O Control States I/O Control

Register State (Binary)

IOIX

=

^LSB Control Definition Logic Term

I03X = MSB

a

None None

I Control output COXX/

2 Data output DOXX/

3 Space serial Teletype SPI

4 Concurrent I/O acknowledge CACK/

5 Interrupt acknowledge IACK/

6 Data input DIXX/

7 Spare SP3/

4.2.4.2 Lines CPHI and CPH2/.

These lines provide processor clock signals to device controllers. Each line can be used independently as a 5 MHz square wave source, or the lines may be NANDed together to produce a 33-nanosecond clock pulse (CPHI is inverted and delayed approximately 33 nanoseconds to form CPH2/). The relationship of the signals on lines CPHI and CPH2/ is shown in Figure 4-2.

/""' .. - - - 200 NS - - - -.. ""'1

CPH1

---.1 __ - ^I

CPH2/

J ^I--

APPROXIMATELY 33 NS

U U

I..

200 NS - - - , -.... """1

Figure 4-2. Relationship of Control Signals CPHI and CPH2/

4.2.4.3 Control Line MRST/

This line is the master reset line which is activated by the front panel RESET switch, or by the power fail or restart. It is used to clear all control flip-flops to their initialized condition. Ground potential is applied to this line when the RESET switch is pressed.

4.2.4.4 Control Line PROT/, PRIN/

This line carries interrupt request priority from controller to controller along the CPU backplane. The line is labeled PROT/ (priority Out) as it leaves the CPU and each controller, and enters each controller as term PRIN/ (Priority In).

Relative priority of each controller is determined by the positions of the controller boards. The first controller in the mainframe (nearest the CPU) has highest mainframe priority with the last controller having lowest main-frame priority.

4.2.4.5 Spare Lines

Spare lines SP2 and SP7 are applied to the byte I/O bus. They are provided only for special requirements and are not terminated in any way on the standard Micro-One.

4.2.4.6 Control Line SELO/, SELI/.

This line carries external interrupt and concurrent I/O select priority from controller to controller along the CPU backplane. It is labeled SELO/

(Select Out), as it leaves the CPU, and each controllers, and enters each controller as term SELl/ (Select In).

Selection priority of the controllers is determined by the positions of the controller boards in the mainframe and expansion chassis (para 4.2.4.4).

NOTES

• A controller must receive PRIN/ to make an external interrupt request. The requesting controller removes PROT/ from all lower priority controllers to lock out lower priority interrupt requests. The requesting controller must receive SELl/ from the preceding controller to respond to an interrupt acknowledg-ment (lACK/).

• Any controller can make a concurrent I/O request (ECIOI) at any time. Simultaneous concurrent requests are handled in order of priority as a requesting controller must receive SELI/

in order to respond to the concurrent I/O acknowledgment (CACK/).

A controller requesting a concurrent I/O transfer will not pass SELO/ to the next controller until it has transferred one data byte.

• Descriptions of the PROT/, PRIN/, SELO/, and SELI/ functions are provided in paragraphs 4.6 through 4.6.3.

4-5

Dans le document MICRO-ONE I (Page 83-88)