COMPONENT inter

inter

COMPONENT DATA CATALOG

JANUARY 1982

Intel Corporation makes no warranty for the use of its products and assumes no responsibility for any errors which may appear in this document nor does it make a commitment to update the information contained herein.

The following are trademarks of Intel Corporation and may only be used to identify Intel Products:

BXp, CREDIT, i, ICE, iCS, im , iMMX, Insite, Intel, intel, Intelevision, Intellec, iOSP, iRMX, iSBC, iSBX, Library Manager, MeS, Megachassis, Micromainframe, Micromap, Multimodule, Plug-A-Bubble, PROMPT, RMX/80, System 2000 and UPI.

MDS is an ordering code only and is not used as a product name or trademark. MDS" is a registered trademark of Mohawk Data Sciences Corporation .

• MUL TIBUS is a patented Intel bus.

Additional copies of this manual or other Intel literature may be obtained from:

© INTEL CORPORATION, 1981

Intel Corporati on

Literature Department SV3-3 3065 Bowers Avenue Santa Clara, CA 95051

Table of Contents·

Alphanumeric Index ...••••...•••...•..•••••••••.••••••••..••....•.•.•. v CHAPTER 1

Random Access Memory

2114A, 1024 x 4-Bit Static RAM ... 1-1 2115A, 2125A Family, High Speed 1K x 1-Bit Static RAM... 1-5 2115H, 2125H Family, High Speed 1K x H3it Static RAM... 1-10 2118 Family 16,384 x 1-Bit Dynamic RAM ... 1-15 2128 2K x 8 Static RAM.. ... ... .. ... ... ... ... .. ... 1-26 2141,4096 x 1-Bit Static RAM... ... 1-30 2142,1024 x 4-Bit Static RAM ... 1-36 2147A, 1K x 4 Static RAM... 1-40 2147H High Speed 4096 x 1-Bit Static RAM... ... ... 1-44 2148H, 1024 x 4-Bit Static RAM ... ,. .. ... . ... ... ... ... 1-48 2149H, 1024 x 4-Bit Static. RAM.... ... ... ... 1-52 2164 Family 65,536 x 1-Bit Dynamic RAM... ... ... ... ... .. ... 1-56 2164-25,65,536 x 1-Bit Dynamic RAM ... , ... ,.. .. ... 1-64 2167 High Speed 16,384 x 1-Bit Static RAM... 1-72 2186/7,8192 x 8-Bit Integrated RAM... ... .. ... ... 1-77 8148, 4096 x 8-Bit Integrated RAM ... 1-76 CHAPTER 2

Read Only Memory and Memory Support

2716, 16K (2K x 8) UV Erasable PROM... 2-1 2732A, 32K (4K x 8) UV Erasable PROM ... 2-9 2764, (8K x 8) UV Erasable PROM... .. ... ... ... ... .... 2-16 27128. (16K x 8) UV Erasable PROM.. ... ... ... ... ... ... .. ... 2-22 2815, 16K (2K x 8) Electrically Erasable PROM ... 2-23 2816, 16K (2K x 8) Electrically Erasable PROM... ... ... ... ... .. ... .. ... 2-36 2817. 16K (2K x 8) Electrically Erasable PROM... ... ... ... .. ... .. ... . 2-49 3628A, 8K (1 K x 8) Bipolar PROM ... :... 2-50 3632, 32K (4K x 8) Bipolar PROM ... '.' . . . 2-53 3636B, 16K (2K x 8) Bipolar PROM ... 2-56 82S181/82HS181, 8K (1 K x 8) Bipolar PROM ... 2-59 82S191/82HS191, 16K (2K x 8) Bipolar PROM... 2-62 82S321/82HS321, 32K (4K x 8) Bipolar PROM ... 2-65 Bipolar PROM Programming. . . 2-68 Bipolar PROM Cross Reference. . . 2-71 CHAPTER

3

Magnetics

BPK70,1 Mbit Bubble Storage Subsystem... .. ... ... ... 3-1 BPK72 Bubble Storage Prototype Kit. . . ... . . . .. . . .. . . 3-3 7110, 1 Megabit Bubble Memory Family ... 3-5 7220-1 Bubble Memory Controller. . . .. . . ... . . 3-11 7230 Current Pulse Generator for Bubble Memories ... 3-26 7242 Dual Formatter/Sense Amplifier for Bubble Memories. . . 3-30 7250 Coil Pre-Driver for Bubble Memories ...•.. 3-40 7254 Quad VMOS Drive Transistors for Bubble Memories ... 3-44 CHAPTER 4

Telephony and Signal Processing

2910A PCM Codec-IL Law, 8-Bit Companded

NO

and D/A Converter... 4-1 2911 A PCM Codec-A Law, 8-Bit Companded

NO

and D/A Converter ... 4-16 2912A PCM Transmit/Receive Filter . . . .. . . 4-30

2913/2914 Combined Single Chip... ... 4-42 2921 ... 4-60 CHAPTER 5

Automotive

P80A48H/P80A35HL HMOS Single Component 8-Bit Microcomputer ... ,... 5-1 P80A49H/P80A39HL HMOS Single Component 8-Bit Microcomputer... 5-17 P80A48L HMOS Single Component 8-Bit Microcomputer. . . .. . . 5-9

CHAPTER 6

MCS-48™ Microprocessors

8020H HMOS Single-Component 8-Bit Microcomputer... 6-1 8021 Single Component 8-Bit Microcomputer ... 6-7 8021 H HMOS Single Component 8-Bit Microcomputer ... . . . . .. . . 6-8 8022 Single Component 8-Bit Microcomputer with On-Chip

NO

Converter... 6-17 8022H High Performance Single Component 8-Bit Microcomputer with On-Chip

NO

Converter 6-23 8031/8051/8751 Single-Component 8-Bit Microcomputer ... 6-24 8048H/8048H-1/8035HU8035HL-1 HMOS Single Component 8-Bit Microcomputer... 6-39 80C48/80C35 CHMOS Single-Component 8-Bit Microcomputer ... 6-46 8748H/8035H HMOS Single-Chip EPROM Microcomputer ... 6-53 8049H/8049HL HMOS Single-Component 8-Bit Microprocessor ... 6-62 80C49/80C39 CHMOS Single-Component 8-Bit Microcomputer... ... 6-69 8749H/8749H-8/8739H/8739H-B . . . . .. . . ... .. . . .. . . . .. . .. . .. .. ... . . 6-76 8243 MCS-48 Input/Output Expander . . .. .. . .. . .. .. . . .. .. . . .. . .. . . .. . . 6-85 8050H/8040H HMOS Single Component 8-Bit Microcomputer. . . 6-91 CHAPTER 7

MCS-80/85™ Microprocessors

8080N8080A-1/8080A-2, 8-Bit N-Channel Microprocessor ... 7-1 8085AH/8085AH-2 Single Chip 8-Bit HMOS Microprocessors... ... 7-10 8085N8085A-2 Single Chip 8-Bit N-Channel Microprocessors ... 7-26 8155H/8156H/8155H-2/8156H-2, 2048 Bit Static HMOS RAM with I/O Ports and Timer... 7-30 8155/8156/8155-2/8156-2,2048 Bit Static MOS RAM with I/O Ports and Timer... 7-42 8185/8185-2, 1024 x 8-Bit Static RAM for MCS-85 ... 7-45 8205 High Speed 1 Out of 8 Binary Decoder. . . 7-50 8212 8-Bit Input/Output Port... ... 7-55 8216/8226, 4-Bit Paraliel Bidirectional Bus Driver... ... 7-63 8218/8219 Bipolar Microcomputer Bus Controliers for MCS-80 and MCS-85 Families... ... 7-68 8224 Clock Generator and Driver for 8080A CPU ... 7-79 8228/8238 System Controlier and Bus Driver for 8080A CPU. . . 7-84 8237N8237A-5 High Performance Programmable DMA Controlier . . . 7-88 8257/8257-5 Programmable DMA Controlier ... 7-103 8259N8259A-2/8259A-8 Programmable Interrupt Controlier . .. . .. . .. . .. . . .. ... . . ... 7-120 8355/8355-2, 16,384-Bit ROM with I/O ... 7-138 8755N8755A-2, 16,384-Bit EPROM with I/O ... 7-146 CHAPTER 8

IAPX 86, 88 Microprocessors

iAPX 86/10 16-Bit HMOS Microprocessor... ... ... 8-1 iAPX 88/10 8-Bit HMOS Microprocessor... ... ... ... ... ... 8-25 8089 8/16-Bit HMOS I/O Processor... ... .... ... ... 8-52 iAPX 86/20, 88/20, 8-Bit HMOS Numeric Data Processor. . . .. . . . .. . . .. . . .. . . 8-66 iAPX 86/30, iAPX 88/30 Operating System Processors... ... 8-86 8282/8283 Octal Latch . . . .. .. . .. . . .. .. .. . .. . .. . . • .. . .. .. . .. . .. . . .. . .. . . .. 8-108 8284A Clock Generator and Driver for iAPX 86/10, iAPX 88/10 8089 Processors ... 8-113

ii

8286/1287 Octal Bus Transceiver ...•... 8-121 8288 Bus Controller for iAPX 86/10, iAPX 88/108089 Processors ... 8-126 8289 Bus Arbiter ... 8-133

CHAPTSl9

MicropDcessor Peripherals Slave Processors

8041 ~Hl8041AH-2/8641N8741A Universal Peripheral Interface 8-Bit Microcomputer ... . 8042/$742 Universal Peripheral Interface 8-Bit Microcomputer ... . 8231 i. Arithmetic Processing Unit ... . 8232 Floating Point Processing Unit ... . 8294 Data Encryption Unit ...•...•

8295 Dot Matrix Printer Controller ... . Memny Controllers

8202.\ Dynamic RAM Controller ... . 8203-64K Dynamic RAM Controller ... . 8206 Error Detection and Correction Unit ... . 8271a271-6 Programmable Floppy Disk Controller ... . 8272 Single/Double Density Floppy Disk Controller ... . DataCommunications

9-1 9-14 9-27 9-37 9-49 9-60 9-69 9-83 9-98 9-117 9-146 8251" Programmable Communications Interface.. ... .. . .. . ... .. ... .. .... 9-165 8256 Multifunction Universal Asynchronous Receiver-Transmitter (MUART) ... 9-182 8273, 8273-4, 8273-8 Programmable HDLC/SDLC Protocol Controller ... 9-191 8274 Multi-Protocol Serial Controller. ... . .. ... .. . .. .. .... .... ... ... . ... ... 9-216 8291A GPIB Talker/Listener ...•... 9-251 829~ GPIB Controller ... 9-280 829S GPIB Transceiver ... 9-295 Contrqllers

8253/8253-5 Programmable Interval Timer ... . 8254 Programmable Interval Timer ...•

8255N8255A-5 Programmable Peripheral Interface ...•.•...

8275 Programmable CRT Controller ... . 8276 Small System CRT Controller ... . 8279/8279-5 Programmable Keyboard/Display Interface ... .

CHAPTER 10

IAPX 432 MICROMAINFRAME™

9-307 9-318 9-333 9-354 9-378 9-395

iAPK 43201/43202/43203 VLSI Micromainframe System ... 10-1 iAPX 43201, 43202 VLSI General Data Processor... ... 10-3 iAPX 43203 VLSI Interface Processor. .. . . .. ... .. . .. .. ... . .. .. ... .... .. ... ... .. ... 10-34

CHAPTER 11

Industrial Grade Products

12114A, 1024 x 4-Bit Static RAM... 11-1 12118 Family 16,384 x 1-Bit Dynamic RAM ... 11-4 12716 Industrial Grade 16K (2K x 8) UV Erasable PROM ... "... 11-9 18022 Single Component 8-Bit Microcomputer with On-Chip

ND

Converter ... , ... 11-13 18031/8051 Single Component 8-Bit Microcomputer ... , ... 11-16 18048H New High Performance HMOS Single Component 8-Bit Microcomputer .. , .. , ... 11-17 18049H/8039H New High Performance Single Coniponent8~Bit Microcomputer. . . .. 11-20 18085AH Single Chip 8-Bit N-Channel Microprocessor ... 11"23 Industrial iAPX 86/10 16-Bit HMOS Microprocessor .. . . .. . . .. . .. 11-27 18155/6H, 2048 Bit Static MOS RAM with I/O Ports and Timer ... : ... '. . . . . .. 11-37 18185,1024 x 8-Bit Static RAM for MC5-85 ... 11-40 18212, 8-Bit Input/Output Port ... 11-45 18216/8226, 4-Bit Parallel Bidirectional Bus Driver ... 11-48

18259A Programmable Interrupt Controller ... .

i: ... ' ...

^11-51

18282/8283 Octal Latch ... ; ... ,.; ... :.; ... 11-57 18284 Clock Generator and Driver for iAPX 86, 88 Processors ... '... 11-61 18286/8287 Octal Bus Transceiver. ... . .. .. . ... ... . ... . . .... . .. ... . .. .. .. . .. .. ... . . ... .. 11-65 18288 Bus Controller for iAPX 86, 88 Processors ... i.. •• 11 ~70 18289 Bus Arbiter ... :... 11-75 18355, 16,384-Bit ROM with I/O ... '. ,. .. 11-79 18755A, 16,384-Bit EPROM with I/O ...•... , ... , .. ; ... 11-82 CHAPTI;R12

Military Grade Products

'Introduction. . .. . . .. . .. . ... . .. . . ... . ... .. ... .. .. . ... . . . ... ... . .. .. . .. . .. .. . . ... ... 12-1 M2114A, 1024 x 4-Bit Static RAM ... 12-4 M2118 Family 16,384 x 1-Bit Dynamic RAM ... '," 12-8 M2147H High Speed 4096 x 1-Bit Static RAM ...•... : .. 12-13 M2148H HighSpeed 1024 x 4-Bit Static RAM ... , ... 12-17 M2167 ... .. 12-21 M2716/M2716M, 16K (2K x 8) UV Erasable PROM ... ; ... , ... :.. 12-25 M2732, 32K (4K x 8) UV Erasable PROM ... ; ....••...•... 12-28 M2764 ... 12-29 M2816, 16K (2K x 8) Electrically Erasable PROM ...•... 12-33 M3632 ... : .. , ... 12-38 M3636, 16K (2K x8) Bipolar PROM ... : ... : .. ,' ... 12-39 M8048/M8748/M8035L Single Component 8-Bit Microcomputer ... 12-42 M8080A, 8-Bit N-Channel Microprocessor ... 12-48 M8085AH Single Chip 8-Bit N-Channel Microprocessor ... 12-53 Military iAPX 86/10, 16-Bit HMOS Microprocessor. . ... .. . ... . .. . .. . .. .. . .. . . ... . .... ... .12-58 M8155H, 2048-Bit Static MOS RAM with I/O Ports and Timer ... 12-67 M8185, 1024 x 8-Bit Static RAM for MCS-85 ... 12-70 . M8212, 8-Bit Input/Output Port ... ; ... 12-72 M8214 Priority Interrupt Control Unit. . .. .... . .. . .. . ... .. . ... . .. . .. ... .. .. . .. .. . . . ... . .... 12-76 M8216/M8226, 4-Bit Parallel Bidirectional Bus Driver ... :. 12-79 M8224 Clock Generator and Driver for 8080A CPU ... ; ... 12-82 M8228 System Controller and Bus Driver for M8080A CPU ... 12-87 M8231A Arithmetic Processing Unit ... : ... ~. . .. . .. . ... . . ... . .... .. 12-92 M8243 MCS-48 Input/Output Expander ... 12-95 M8251A Programmable Communication Interface ... 12-98 M8253 Programmable Interval Timer ... '.12-102 M8255A Programmable Peripheral Interface ... , ... 12-106 M8257 Programmable DMA Controller ... ; ... 12-112 M8259A Programmable Interrupt Controller ...•...•... 12-116 M8282/8283 Octal Latch ... 12-119 M8284 Clock Generator and Driver for Military iAPX 86 ... ;; •.. 12-122 M8286/8287 Octal Bus Transceiver ... , ... 12-125 M8288 Bus Controller for Military iAPX 86 ... 12-128 M8289 Bus Arbiter ... ~ ... 12-133 M8741A Universal Peripheral Interface 8-Bit Microcomputer ... 12-136 M8755A, 16,384-Bit EPROM with I/O ... ~ ... 12-140 CHAPTER 13

Quality Assurance ... : •.•.• ~... .•••••••••• 13-1

CHAPTER 14

General Information

Ordering Information ... '.' ... , .. .. ... .•.. . .... . ... . . . 14-1 Packaging Information ... 14-2 MicrocomputerWorkshops ...•...•... 14-11 Product Service ... 14-14

iv

Alphanumeric Index

2114A, 10a x 4-Bit Static RAM ... 1-1 12114A,104x4-BitStaticRAM ... 11-1 M2114A, 1124 x 4-Bit Static RAM ... 12-4 2115A, 215A Family, High Speed 1K x 1-Bit Static RAM ... 1-5 2115H, 215H Family, High Speed 1K x 1-Bit Static RAM ... 1"10 2118 Famr 16,384 x 1-Bit Dynamic RAM ... 1-15 12118 Farny 16,384 x 1-Bit Dynamic RAM... 11-4 M2118 Falily 16,384 x 1-Bit Dynamic RAM ... 12-8 2128 2K xl Static RAM ... 1-26 2141, 4094x 1-Bit Static RAM ... 1-30 2142, 102.x 4-Bit Static RAM ... ,... 1-36 2147A,1Hx4StaticRAM ... 1-40 2147H Higl Speed 4096 x 1-Bit Static RAM ... 1-44 M2147H Hgh Speed 4096 x 1-Bit Static RAM ... 12-13 2148H, 1124 x 4-Bit Static RAM ... 1-48 M2148H Hgh Speed 1024 x 4-Bit Static RAM ... 12-17 2149H, 1~4 x 4-Bit Static RAM ... 1-52 2164 Famly 65,536 x 1-Bit Dynamic RAM ... 1-56 2164-25,6,536 x 1-Bit Dynamic RAM ... 1-64 2167 HigtSpeed 16,384 x 1-Bit Static RAM ... 1-72 M2167 ... 12-21

~186/7, 8~2 x 8-Bit Integrated RAM ... 1-77 . 27128, (18< x 8) UV Erasable PROM.... .. ... .... ... ... ... ... .... .. .... ... ... .. .... 2-22 2716, 16K(2K x 8) UV Erasable PROM ... 2-1 1271-6 Indlstrial Grade 16K (2K x 8) UV Erasable PROM ... 11-9 M2716/Ml716M, 16K (2K x 8) UV Erasable PROM ... 12-25 2732A, 3a< (4K x 8) UV Erasable PROM ... 2-9 M2732, 3lK (4K x 8) UV Erasable PROM ... 12-28 2764, (8Kx 8) UV Erasable PROM ... 2-16 M2764 ... ,.... 12-29 2815, 16K(2K x 8) Electrically Erasable PROM ... 2-23 2816, 16K (2K x 8) Electrically Erasable PROM ... 2-36 M2816, 11K (2K x 8) Electrically Erasable PROM ... 12-33 2817, 16K(2K x 8) Electrically Erasable PROM ... 2-49 2910A PGM Codec - /L Law, 8-Bit Companded A/D and D/A Converter ...•... 4-1 2911 A PCM Codec - A Law, 8-Bit Companded A/D and D/A Converter ... , ... , 4-16 2912A PCM Transmit/Receive Filter ... 4-30 2913/291+ Combined Single Chip ... 4-42 2921 '" ... 4-60 3628A, 8K (1 K x 8) Bipolar PROM ... 2-50 3632, 32K (4K x 8) Bipolar PROM ... 2-53 M3632 . ... 12-38 3636B, 16K (2K x 8) Bipolar PROM ... 2-56 M3636, 16K (2K x 8) Bipolar PROM ... 12-39 iAPX 43201/43202/43203 VLSI Micromainframe System ... 10-1 iAPX 43201, 43202 VLSI General Data Processor ... 10-3 iAPX 43203 VLSI Interface Processor ... 10-34 7110,1 Megabit Bubble Memory Family ... 3-5 7220-1 Bubble Memory Controller ... 3-11 7230 Current Pulse Generator for Bubble Memories ... 3-26 7242 Dual Formatter/Sense Amplifier for Bubble Memories ... 3-30 7250 Coil Pre-Driver for B.ubble Memories ... 3-40 7254 Quad VMOS Drive Transistors for Bubble Memories ... 3-44 8020H HMOS Single-Component 8-Bit Microcomputer ... 6-1 8021 Single Component 8-.Bit Microcomputer. . . .. 6-7

v

8021 H HMOS Single-Component 8-Bit Microcomputer. ; ... c ; • • • • • • • • • • • • • • • • • • • • • • • • • • • •• • • • • • • 6-8 8022 Single Component 8-Bit Microcomputer with On-Chip A/D Converter ... 6-17 8022H High Performance Single Component 8-Bit Microcomputer with On-Chip A/D Converter. . . . .6-23 18022 Single Component 8-Bit Microcomputer with On-ChipA/D Converter ... 11-13 8031/8051/8751 Single Component 8-Bit Microcomputer ...•... ;... 6-24 18031/8051 Single Component 8-Bit Microcomputer .... ,.; ... 11-16 8041 AH/8041AH-2/8641N8741 A Universal Peripheral Interface 8-Bit Microcomputer ... 9-1 8042/8742 Universal Peripheral Interface 8-Bit Microcomputer ...•... 9-14 80C48/80C35 CHMOS Single-Component 8-Bit Microcomputer .. 7':... 6-46 8048H/8048H-l/8035HL/8035HL-l HMOS Single Component 8-Bit Microcomputer ... 6-39 18048H NewHigh Performance HMOS Single Component 8-Bit Microcomputer ... ; ... 11-17 M8048/M8748/M8035L Single Component 8-Bit Microcomputer ... : ... 12-42 P80A48H/P80A35HL HMOS Single Component 8-Bit Microcomputer ... 5-1 P80A48L HMOS Single Component 8-Bit Microcomputer ... , ... 5~17 80C49/80C39 CHMOS Single-Component 8-Bit Microcomputer ... :.... 6-69 8049H/8049HL HMOS Single Component 8-Bit Microprocessor ... 6-62 18049H/8039H New High Performance Single Component 8-Bit Microcomputer ... , ... 11"20 P80A49H/P80A39HL HMOS Single Component 8-Bit Microcomputer ....•... ;... 5-9 8050H/8040H HMOS Single Component 8-Bit Microcomputer ... .6-91 8080N8080A-1/8080A-2, 8-Bit N-ChanneiMicroprocesser ... ; ... ;. .7-1 M8080A, 8-Bit N-Channel Microprocessor ... .'... .12-48 8085N8085A-2 Single Chip 8-Bit N-Channel Microprocessors ... . . .. 7-26 8085AH/8085AH-2 Single Chip 8-Bit HMOS Microprocessors ... 7-10 18085AH Single Chip 8-Bit N-Channel Microprocessor ... .11-23 M8085AH Single Chip 8-Bit N-Channel Microprocessor ... 12~53 iAPX 86/10 16-Bit HMOS Microprocessor ... 8-1 Industrial iAPX 86/10 16-Bit HMOS Microprocessor ... :... 11-27 iAPX 86/20, 88/20 8-Bit HMOS Numeric Data Processor ... : . .. . . .. . . .. . . .. ... 8-66 iAPX 86/30, iAPX 88/30 Operating System Processors ... o'... 8-86 iAPX 88/10 8-Bit HMOS Microprocessor ... 8-25 8089 8/16-Bit HMOS I/O Processor ... 8-52 8148,4096 x 8-Bit Integrated RAM ... 1-76 8155/8156/8155-2/8156-2, 2048 Bit Static MOS RAM with I/O Ports and Timer ... ... 7-42 8155H/8156H/8155H-2/8156H-2, 2048 Bit Static HMOS RAM with I/O Ports and Timer ... 7-30 18155/6H, 2048 Bit Static MOS RAM with I/O Ports and Timer ... 11-37 M8155H, 2048-Bit Static MOS RAM with I/O Ports and Timer ... 12-67 8185/8185-2,1024 x 8-Bit Static RAM for MCS-85 ... ; ... 7-45 18185,1024 x 8-Bit Static RAM for MCS-85 ; ... ; ... 11-40 M8185, 1024 x 8-Bit Static RAM for MCS-85 ... 12-70 8202A Dynamic RAM Controller ...•... ;... 9-69 8203 64K Dynamic RAM Controller ... , .. , ... , " .... .... .. ... . .. 9-83 8205 High Speed lOut of 8 Binary Decoder ... ;... 7-50 8206 Error Detection and Correction Unit ... , .... ,... . . .. . . 9-98 8212 8-Bit Input/Output Port ... " ... '" ... . . .. .. .. .. .. .. . ... . . 7-55 18212, 8-Bit Input/Output Port ... ; ... ; ...•... ~ . . ... 11-45 M8212, 8-Bit Input/Output Port... .12-72 M8214 Priority Interrupt Control Unit ... ,. ; ... 12-76 8216/8226, 4-Bit Parallel Bidirectional Bus Driver ... ' ... c • • • • • • • , • • • • • • • • • • • • • • • • • . • • • 7-63 18216/8226, 4-Bit Parallel Bidirectional Bus Driver ... ;... 11-48 82S181/82HS181, 8K (1 K x 8) Bipolar PROM ... .' ... c . . . 2-59 82S191/82HS191, 16K (2K x 8) Bipolar PROM ... 2-62 82S321/82HS321, 32K (4K x 8) Bipolar PROM ... : ... c . . . 2-65 M8216/M8226, 4-Bit Parallel Bidirectional Bus Driver ... :.: ... ; :; ... ' ... , ... 12-79 8218/8219 Bipolar Microcomputer Bus Controllers for MCS-80 and MCS-85 Families ; ... 7-68 8224 Clock Generator and Driver for 8080A CPU ... : ... : ... ;... 7-79 M8224 Clock Generator and Driver for 8080A CPU ... ; •... : ... :... 12-82 8228/8238 System Controller and Bus Driver for 8080A CPU ... ;... 7-84 M8228 System Controller and Bus Driver for M8080A CPU ... 12-87

vi

8231 A Arithmetic Processing Unit ... 9-27 M8231 A Arithmetic Processing Unit ... 12-92 8232 Floating Point Processing Unit ... 9-37 8237N8237A-5 High Performance Programmable DMA Controller. .. . . . .. . . .. . .. . .. . .. . .. . . .. 7-88 8243 MCS-48 Input/Output Expander ... ' " 6-85 M8243 MCS-48 Input/Output Expander ... 12-95 8251 A Programmable Communication Interface... 9-165 M8251 A Programmable Communication Interface ... 12-98 8253/8253-5 Programmable Interval Timer ... 9-307 M8253 Programmable Interval Timer... ... ... 12-102 8254 Programmable Interval Timer ... 9-318 8255N8255A-5 Programmable Peripheral Interface ... 9-333 M8255A Programmable Peripheral Interface ... 12-106 8256 Multifunction Universal Asynchronous Receiver-Transmitter (MUART) ... 9-182 8257/8257-5 Programmable DMA Controller ... 7-103 M8257 Programmable DMA Controller ... 12-112 8259N8259A-218259A-8 Programmable Interrupt Controller ... 7-120 18259A Programmable Interrupt Controller ... 11-51 M8259A Programmable Interrupt Controller ... 12-116 8271/8271-6 Programmable Floppy Disk Controller.. . ... . . . .. ... . . .. .. . .. .. . . .. . . .. . . .. .. 9-117 8272 Single/Double Density Floppy Disk Controller ... 9-146 8273, 8273-4, 8273-8 Programmable HDLC/SDLC Protocol Controller ... 9-191 8274 Multi-Protocol Serial Controller ... 9-216 8275 Programmable CRT Controller ... 9-354 8276 Small System CRT Controller ... . . . .. 9-378 8279/8279-5 Programmable Keyboard/Display Interface ... 9-395 828218283 Octal Latch ... 8-108 18282/8283 Octal Latch ... 11-57 M8282/8283 Octal Latch ... 12-119 8284A Clock Generator and Driver for iAPX 86/10, iAPX 88/10 8089 Processors ... 8-113 18284 Clock Generator and Driver for iAPX 86, 88 Processors ... 11-61 M8284 Clock Generator and Driver for Military iAPX 86 ... 12-122 8286/8287 Octal Bus Transceiver ... 8-121 18286/8287 Octal Bus Transceiver ... 11-65 M8286/8287 Octal Bus Transceiver ... 12-125 8288 Bus Controller for iAPX 86/10, iAPX 88/10 8089 Processors ... 8-126 18288 Bus Controller for iAPX 86, 88 Processors ... 11-70 M8288 Bus Controller for Military iAPX 86 ... _ ... _ .... _ .. _... 12-128 8289 Bus Arbiter ... 8-133 18289 Bus Arbiter ... 11-75 M8289 Bus Arbiter ... 12-133 8291 A GPIB Talker/Listener ... 9-251 8292 GPIB Controller ... 9-280 8293 GPIB Transceiver ... __ .. _ ... _ . . . .. 9-295 8294 Data Encryption Unit ... 9-49 8295 Dot Matrix Printer Controller ... 9-60 8355/8355-2, 16,384-Bit ROM with I/O ... 7-138 18355, 16,384-Bit ROM with I/O ... 11-79 M8741 A Universal Peripheral Interface 8-Bit Microcomputer ... 12-136 8748H/8035H HMOS Single-Chip EPROM Microcomputer ... 6-53 8749H/8749H-8/8739H/8739H-B ... 6-76 8755N8755A-2, 16,384-Bit EPROM with I/O ... 7-146 18755A, 16,384-Bit EPROM with I/O ... 11-82 M8755A, 16,384-Bit EPROM with I/O ... 12-140 Bipolar PROM Cross Reference ... 2-71 Bipolar PROM Programming ... 2-68 BPK70,1 Mbit Bubble Storage Subsystem ... 3-1 BPK72 Bubble Storage Prototype Kit ... 3-3

Random Access

Memory 1

inter

2114A

1024 X 4 BIT STATIC RAM

2114AL·1 2114AL·2 2114AL·3 2114AL·4 2114A·4 2114A·5

l

Max. Access Time (ns) 100 120 150 200 200 250

I

Max. Current (mA) 40 40 40 40 70 70

• HMOS Technology • Completely Static Memory - No Clock

• Low Power, High Speed or Timing Strobe Required

• Directly TTL Compatible: All Inputs

• Identical Cycle and Access Times and Outputs

Single +5V Supply ±10% • Common Data Input and Output Using

• Three-State Outputs

• High Density 18 Pin Package • 2114 Upgrade

The Intell8 2114A is a 4096-bit static Random Access Memory organized as 1024 words by 4-bits using HMOS, a high per- formance MOS technology. It uses fully DC stable (static) circuitry throughout, in both the array and the decoding, therefore it requires no clocks or refreshing to operate. Data access is particularly simple since address setup times are not required. The data is read out nondestructively and has the same polarity as the input data. Common input/output pins. are provided.

The 2114A is designed for memory applications where the high performance and high reliability of HMOS, low cost, large bit storage, and simple interfacing are important design objectives. The 2114A is placed in an 18-pin package for the highest possible density.

It is directly TTL compatible in all respects: inputs, outputs, and a single +5V supply. A separate Chip Select (CS) lead allows easy selection of an individual package when outputs are or-tied.

PIN CONFIGURATION LOGIC SYMBOL BLOCK DIAGRAM

0

_.J]Lvcc

As ^Vee Ao ^A3 _{A ®}

~GND

As ^A, A, I/0,

• ₀

A. As ROW MEMORY ARRAY

A. As

CD

^{SELECT 64 ROWS}

A:t As@ 64 COLUMNS

A3 Ag 110,

A. A,

Ao ^{110, @}

As ^A.

A, 110, A. 1103

A:t 110, A:t

CS 110. A. 110.

GND WE As

WE CS

PIN NAMES

An-A. ADDRESS INPUTS Vee POWER (+5V)

o .

PIN NUMBERS

-~ WRITE ENABLE GNDGROUND

CI CHIP SELECT

I/O, -I/O. DATA INPUT/OUTPUT

INTEL CORPORATION ASSUMES NO RESPONSIBILITY FOR THE USE OF ANY CIRCUITRY OTHER THAN CIRCUITRY EMBODIED IN AN INTEL PRODUCT. NO OTHER CIRCUIT PATENT LICENSES ARE IMPLIED.

2114A FAMILY ABSOLUTE MAXIMUM RATINGS·

Temperature Under Bias ...•.•.... -10°C to 80°C Storage Temperature ...•... -65°C to 150°C Voltage on any Pin

With Respect to Ground ...•.•...•..•. . -3;5\1 to+7V Power Dissipation .•... 1.0W D.C. Output Current •...•...•...•.... 5mA

D.C. AND OPERATING CHARACTERISTICS

TA

=

O°C to 70°C,

Vee =

^5V ± 10%, unless otherwise noted.

2114At.-1/L-2/L-3/L-4

SYMBOL PARAMETER Min. Typ.lll

IILII Input Lead Current (All Input Pins)

IlLOI

^1/0 Leakage Current

ICC Pewer Supply Current 25

V IL Input Lew Voltage -3.0 VIH Input High Veltage 2.0 10L Output Lew Current 2.1 9.0 10H Output High Current -1.0 -2.5 105 121 Output Shert Circuit

Current

NOTE: 1. Typical values are for T A = 25' C and Vee = ^5.o.V.

2. Duration not to exceed 30 seconds.

CAPACITANCE

TA" 25°C, f = 1.0 MHz

SYMBOL TEST

CliO Input/Output Capacitance CIN Input Capacitance

Max.

10 10

40

0.8 6.0

40

MAX 5 5 NOTE: This parameter is periodically sampled and not ,10.0.% tested.

A.C. CONDITIONS OF TEST

·COMMENT: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.

,This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections. of this specification is not implied. Ex- posure is not implied. Exposure to absolute maximum rating conditions for extended' periods may affect device reliability.

2114A-4/-5

Min. Typ.lll Max. UNIT CONDITIONS 10 /lA VIN = 0 to. 5.5V

10 /lA CS =V'H

VIIO = GND to. VCC 50 70: mA

Vee

= max, 11/0 = 0 mA,

TA = O°C

-3.0 0.8 V

2.0 6.0 ,,' V

"

2.1 9.0 mA VOL = O.4V

-1.0 -2.5 mA VOH = 2.4V

40 mA

"

, , '

UNIT CONDITIONS pF VI/O

=

^OV

pF VIN =OV

Input Pulse Levels ... 0.8 Volt to 2.0 Volt Input Rise and Fall Times ... 10 nsec ' Input and Output Timing Levels ... 1.5 Volts Output Load ... 1 TTL Gate and CL

=

^{100 pF}

1-2

2114A FAMILY

A.C. CHARACTERISTICS

TA

=

O'C to 70'C, Vee

=

5V ± 10%, unless otherwise noted.

READ CYCLE [1]

2114AL-1 2114AL-2 2114AL-3 2114A-4/L-4 2114A-S

SYMBOL PARAMETER Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. UNIT

tAC Read Cycle Time 100 120 150 200 250 ns

tA Access Time 100 120 150 200 250 ns

teo Chip Selection to Output Valid 70 70 70 70 85 ns

tcx Chip Selection to Output Active 10 10 10 10 10 ns

toTO Output 3-state from Deselection 30 35 40 50 60 ns

tOHA Output Hold from

Address Change 15 15 15 15 15 ns

WRITE CYCLE [2]

2114AL-1 2114AL-2 2114AL-3 2114A-4/L-4 2114A-S

SYMBOL PARAMETER Min. Max. Min. Mex. Min. Max. Min. Max. Min. Max. UNIT

twe Write Cycle Time 100 120 150 200 250 ns

tw Write Time 75 75 90 120 135 ns

tWR Write Release Time· 0 0 0 0 0 ns

torw Output 3-state from Write 30 35 40 50 60 ns

tow Data to Write Time Overlap 70 70 90 120 135 ns

tOH Data Hold from Write Time 0 0 0 0 0 ns

NOTES:

1. A Read occurs during Ihe overlap of a low Os and a high WE.

2. A Wrlle occurs during Ihe overlap of a low CS and a low WE. tw is measured from Ihe latter of ~ or ~ gOing low 10 the earlier of CS or~ gOing high.

WAVEFORMS

READ CYCLE®

I---.oc---I 1--- •• ---1

ADDRE ..

--'1'---+--'1'---

NOTES: .

3.

wr

is high for a Read Cycle.

4. If Ihe

as

low Iransillon occurs simultaneously with the WE low transition, the output buffers remain in a high impedance stata.

5.

wr

must be high during aU address transilions.

WRITE CYCLE

I---~c---~

ADD"ESS _~---~----

@

~ ~~~~---~~~~~~~

DoUT

mHEm:8---:---+----

' ... I--~-.DH

D,. ----<t:==~~

inteI·

2~ 14~

FAMILY

TYPICAL D.C. AND A.C. CHARACTERISTICS

$ 0 w

~

i

0 z

c $ _w :I!

~

.~ a:

1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 4.50

1.4

NORMALIZED ACCESS TIME VI.

SUPPLY VOLTAGE

4.75 5.00 5.25 VCC(V)

NORMALIZED ACCESS TIME VS.

OUTPUT LOAD CAPACITANCE 5,50

1.3

/-'

1.2

V

'1.1 . , / ",/

1.0

/ f /

0.9 0.8 0.7 100

40

30

150 .200 250 300

OUTPUT SOURCE CURRENT

vs. OUTPUT VOLTAGE .

~ ~

20

10

o o

.~

350

··14

NORMALIZED ACCESS TIME VS.

AMBIENT TEMPERATURE 1.2

1. 1

1.0

^l.----' --

^~

$ '0.9

I

^0.8

0.7 0.6 5

20 40 80

NORMAUZED POWER SUPPLY CURRENT VS. AMBIENT TEMPERATURE 1. 2

1. 1

0

-- --

~ 1.

"

9

I

^o. 8

" o.

o. ⁷

0.6

o. 5

80

.80

1

~ ⁴⁰

20

oV

-- ^t-

20 40 .80

OUTPUT SINK CURRENT VS. OUTPUT VOLTAGE

/v /

/

j

. VOL (V)

..

80

80

o '

inter

2115A, 2125A FAMILY

HIGH SPEED 1K X 1 BIT STATIC RAM

2115AL,2125AL 2115A,2125A 2115AL·2,2125AL·2 2115A·2,2125A·2

I

^{Max. T AA (ns) 45}

I

Max. Icc (mA) 75

• Pin Compatible To 93415A (2115A) And 93425A (2125A)

45 125

• Fan-Out Of 10 TTL (2115A Family) -- 16mA Output Sink Current

• Low Operating Power Dissipation --Max. 0.39mW/Bit (2115AL, 2125AL)

70 70

75 125

• TTL Inputs And Outputs

• Single +5V Supply

• Uncommitted Collector (2115A) And Three-State (2125A) Output

• Standard 16-Pin Dual In-Line Package

The Intel® 2115A and 2125A families are high·speed, 1024 words by 1 bit random access memories. Both open collector (2115A) and three·state output (2125A) are available. The 2115A and 2125A use fully DC stable (static) circuitry through- out - in both the array and the decoding and, therefore, require no clocks or refreshing to operate. The data is read out non- destructively and has the same polarity as the input data.

The 2115AL/2125AL at 45 ns maximum access time and the 2115AL-2/2125AL-2 at 70 ns maximum access time are fully compatible with the industry-produced 1 K bipolar RAMs, yet offer a 50% reduction in power of their bipolar equivalents.

The power dissipation of the 2115AL/2125AL and 2115AL-2/2125AL-2 is 394 mW maximum as compared to 814 mW maximum of their bipolar equivalents. For systems already deSigned for 1 K bipolar RAMs, the. 2115A/2125A and the 2115A-2/2125A-2 at 45 ns and 70 ns maximum access times, respectively, offer complete compatibility with a 20% reduction in maximum power dissipation.

The devices are directly TTL compatible in all respects: inputs, outputs, and a single +5V supply. A separate select (CS) lead allows easy selection of an individual package when outputs are OR-tied.

The 2115A and 2125A families are fabricated with Intel's N-channel MOS Silicon Gate Technology.

PIN CONFIGURATION

os v,,

..

^0,.

A, WE

A,

..

A,

..

A, A,

POUT

..

GNO

..

PIN NAMES

CHIP SELECT I Ao'O . . ADDRESS INPUTS

iit WRITE ENABLE

"'.

DATA INPUT DouT DATA OUTPUT

WOAD

t----

DRIVER

ADDRESS DECODER

.r

1.1 r t

Ao Al A} A] A4

000®®

BLOCK DIAGRAM

3lX3Z ARRAY

I ^j

SENSE AMPS

r---

_CONTROL

AND lOGIC

r-

WRln (SEE TRUTH

DRIVERS

1 - ^TABLEI

1 1

ADDRESS DECODER

t ttl t

_-

A~ AS A7 A8 Ag CS WE 0 1111

@@@@@ ~ @ @

TRUTH TABLE

OUTPUT OUTPUT INPUTS

2115A fAMILY 2125A FAMilY ^MODe CS WE o.N DoUT DoUT

H X HIGH Z NOT SELECTED

l HIGH Z WRITE "0"

l H HIGH Z WRITE "1"

l H X DoUT DoUT READ

(')

2115A, 2125A FAMILY

ABSOLUTE MAXIMUM RATINGS*

Temperature Under Bias . . . -lOoC to +85°C Storage Temperature . . . -65°C to +150°C All Output or Supply Voltages . . . -0.5V to +7V All Input Voltages . . . -0.5V to +5.5V D.C. Output Current . . . 20 mA

D.C. CHARACTERISTlCSll,21 Vee = 5V ±5%, T A = O°c to 75°C

Symbol Test

VOLl 2115A Family Output Low Voltage VOL2 2125A Family Output Low Voltage VIH Input High Voltage

VIL Input Low Voltage IlL Input Low Current IIH Input High Current

IlcEXI 2115A Family Output Leakage Current ilOFFI 2125A Family Output Current (High Z) 105[31 2125A Family Current Short Circuit

to Ground

VOH Family Output High Voltage Power Supply Current:

lee leel: 2115AL, 2115AL·2, 2125AL, 2125AL·2

leC2: 2115A, 2115A·2, 2125A, 2125A·2 NOTES:

Min,

2.1

2.4

'COMMENT: Stresses above those listed under "Absolute Maxi·

mum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability .

Typ. Max. Unit Conditions

0.45 V IOL=16mA

0.45 V 10L = 7 mA V

0.8 V

-0.1 -40 IlA Vee = Max., VIN = 0.4V 0.1 40 IlA Vee = Max., VIN = 4.5V 0.1 100 fJ.A Vee = Max., VOUT = 4.5V 0.1 50 fJ.A Vee = Max., VOUT = 0.5V/2.4V

-100 mA Vee = Max.

V 10H = -3.2 mA

60 75 mA All Inputs Grounded; Output Open

100 125 mA

1. The operating ambient temperature ranges are guaranteed with transverse air flow exceeding 400 linear feet per minute and a two minute warm-up. Typical thermal resistance values of the package at maximum temperature are:

eJA (@400 fPM air flowl = 45°CIW eJA (still air! = 60°CIW

eJC = 25°C/W

2. Typical limits are at Vee =0 5V, T A = +25°e, and maximum loading.

3. Duration of short circuit current should not exceed 1 second.

1-6

2115A, 2125A FAMILY

2115A FAMILY A.C. CHARACTERISTlCS[1.21 vcc = 5V ±5%, T A = O°C to 75°C READ CYCLE

2115Al limits 2115A limits 2115Al·2 limits Symbol Test Min. Typ. Max. Min. Typ. Max. Min. Typ. Max.

tACS Chip Select Time 5 15 30 5 15 30 5 15 30

tRCS Ch ip Select ~ecovery Time 10 30 10 30 10 30

'tAA Address Access Time 30 45 30 45 40 70

Previous Read Data Val id After

10 10 10

tOH Change of Address WRITE CYCLE

Symbol Test Min. Typ. Max. Min. Typ. Max. Min. Typ. Max.

tws Write Enable Time 10 25 10 30 10 25

tWR Write Recovery Time 0 25 0 30 0 25

tw Write Pulse Width 30 20 30 10 30 15

tWSD Data Set·Up Time Prior to Write 0 -5 5 -5

a

-5

tWHD Data Hold Time After Write 5 0 5

a

5

a

tWSA Address Set·Up Time 5

a

5 0 5

a

tWHA Address Hold Time 5

a

5 0 5

a

tWSCS Chip Select Set·Up Time 5 0 5 0 5 0

tWHCS Chip Select Hold Time 5 0 5 0 5

a

A.C. TEST CONDITIONS ALL INPUT PULSES

2115A·2 limits Min. Typ. Max. Units

5 15 40 ns 10 40 ns 40 70 ns

10 ns

Min. Typ. Max. Units 10 40

a

^{45 ns}

50 15 ns

5 -5 ns

5

a

^ns

15 0 ns

5 0 ns

5

a

^ns

5

a

ns

"1' .. / .

f'" _ _ . - - - -. ... - - . . 90%

3IP-\ -:---. --- \1\,;_;;...~10%;;;... ^__

"tND -=- _: : ___ 10ns _.-..; : _ 10ns 4.SV

51 on

READ CYCLE

M2125A

DOUT-~----t 300"

r

~1~6LUOING

SCOPE AND JIG)

AOA9 _ _

~)K\. ____________ _

l - tAA -

DOUl DATA VALID

PROPAGATION DELAY FROM CHIP SELECT

WRITE CYCLE

, . . . - -

~ ________________ JI~

AO Ag

---+--+-+ ...

-'w-

r-+--+--1f----

WE

twso

r--...

!-tws... _ t W H A _

- twscs - - . .

-r-

^tws ~~~I1CS---'

"oUT

·UNg:~~E~.···'l ~

(All ABOVE MEASUREMEriiTS REFERENCED TO 1.SVI

2115A,2125A FAMILY

2125 FAMIL V A.C. CHARACTERISTICS[1.21

READ CYCLE

Vee

=

5V ±5%, T A

=

O°C to 75°C

2125AL Limits 2125A Limits 2125AL·2 Limits 2125A·2 Limits

Symbol Test

tAcs Chip Select Time tZACS Chip Select to HIGH Z tAA Add ress Access Ti me tOH Previous Read Data Valid After

Change of Address WRITE CYCLE

Symbol Test

tzws Write Enable to HIGH Z tWR Write Recovery Time tw Write Pulse Width

twsD Data Set-Up Time Prior to Write tWHD Data Hold Time After Write tWSA Address Set·Up Time tWHA Address Hold Time twses Chip Select Set·Up Time tWHes Chip Select Hold Time

A.C. TEST CONDITIONS

READ CYCLE

4.5V

M2115A

"oUT---.---4

600n

lOOn

30pF (INCLUDING SCOPE AND JIG)

Min; Typ.

5 15 10 30 10

Min. Typ.

10 0 30 20

0 -5

5 0

5 0

5 0

5 0

5 0

AO A, _ _ _

.I)K ... _____________ _

i - t A A - - -

Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max.

30 5 15 30 5 15 30 5 15 40

30 10 30 10 30 10 40

45 30 45 40 70 40 70

10 10 10

Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max.

25 10 30 10 25 10 40

25 0 30 0 25 0 45

30 10 30 10 50 15

5 -5 0 -5 5 -5

5 0 5 0 5 0

5 0 5 0 15 0

5 0 5 0 5 0

5 0 5 0 5 0

5 0 5 0 5 0

ALL INPUT PULSES

~ ~---~

3.5Vp-p

± -. ,_.

; " :

. . .'. ..

- \ -^10% 90%

GND -=- _ .• , ,. _ 10n$

~ ~ ... ^{~ ~ ~} :.'.' .1 .. :

GND --=- -~ }--10ns ~ :_-1Ons

WRITE CYCLE cs

'!

Units ns ns ns ns

Units ns ns ns ns ns ns ns ns ns

DATA VALID

---+--+-!--.I-

'w---'

,-+---4--,....--

WE

PROPAGATION DELAY FROM CHIP SELECT

_lWSA ...

~-- - IWSCS DOUT

jAU ABOVE MEASUREMENTS REFERENCED,TO 1.5V)

1-8

2115A, 2125A FAMILY

2125A FAMILY WRITE ENABLE TO HIGH Z DELAY

5V

750~l

2125A 5pF

LOAD 1

W"ITEENA.~ ~

DOUT "0" LEVel tzws r--~~H-;

DATADUTPUT --';;";=;';;"'--"'F=} ^O.5V

~UT _ _ '~"~"L~E~VE~L~_~

DATA OUTPUT

} O.5V

,-__

.!I~!

2125A FAMILY PROPAGATION DELAY FROM CHIP SELECT TO HIGH Z

cs

CHIP SELECT

~UT

---'1

DATA OUTPUT _ _ ~·'O;..".:;LE;.;V.:;EL:"'-_-"F=

DoUT DATA OUTPUT

"'" LEVEL

(ALL tzxxx PARAMETERS ARE MEASURED AT A DELTA OF O.SV FROM THE LOGIC LEVel AND USING LOAD 1.1

2115A/2125A FAMILY CAPACITANCE* Vee= SV, f = 1 MHz, TA = 2SoC 211SA Family 2125A Family

SYMBOL TEST LIMITS LIMITS

TYP. MAX. TYP. MAX.

CI Input Capacitance 3 S 3 S

Co

Output Capacitance S 8 S 8

"This parameter is periodically sampled and is not 100% tested.

TYPICAL CHARACTERISTICS ICC VS. TEMPERATURE

"0

I--

.,I,SA, J"6A-l r--!'26A. ., ... -

1'-1'--

'00 eo eo

70

I-- Z11IAL. 211&AL·2

- ^~

eo

..

o o 70 20 30 ~ . . eo 70 eo

TEMPERATURE (DCI

"0

'00 eo

1

eo

~ 70

..

eo o

ICCVS. Vee

~

/:2115A. 2115A-2 2126A. 2125A-2

,..,

A116AL.2115AL.2 2125AL. Z125AL·2 TA-'Zfi"C

o

VCCIVI

Printed in U.S.A.lE28611179/PS

UNITS TEST CONDITIONS

pF All Inputs = OV, Output Open pF

cs

= SV, All Other Inputs = OV,

Output Open

ACCESS TIME VS. TEMPERATURE

70

eo

..

!

⁴⁰

~ ³⁰

20

'0 o

.1'5AL'~' 2"!A'2 ,....

^i-'"

- t-2125AL-2,2125A-2

~ ... I--'"

- ^r- _-

^~-

- ^-

t - - 2115AL, 21'SA 21j5AL'

r

^26A

^{I -}

Vee -sv o 70 20 30 U . . eo 70 eo

inter

2115H, 2125H FAMILY

HIGH SPEED 1K X 1 BIT STATIC RAM

2125H·1 2115H·2,2125H·2 2115H·3,2125H·3 2115H·4,2125H·4

I

^{Max. T AA (n5) 20 25 30 35}

I

^Max.

^Icc

^{(mA) 150 125 100 125}

• ^{HMOS n} Technology • TTL Inputs and Outputs

• Pin Compatible to 93415A (2115H) and • Single +5V Supply 93425A (2125H)

• Uncommitted Collector (2115H) and

• 16mA Output Sink Current Three-State (2125H) Output

• Low Operating Power Dissipation • Standard 16-Pin Dual In-Line Package Max. 0.53 mW/Bit (2115H-3, 2125H-3)

The Intel® 2115H and 2125H families are high speed, 1024 words by 1·bit random access memories fabricated with HMOSII, Intel's advanced N-channel MOS silicon gate technology. Both open collector (2115H) and three-state output (2125H) are available. The 2115H and 2125H use fully DC stable (static) circuitry throughout - in both the array and the decoding and, therefore, require no clocks or refreshing to operate. The data is read out non-destructively and has the same polarity as the input data.

HMOS IT's advanced technology allows the production of the industry's fastest, low power, 1 K static RAMs - offering access times as low as 20ns.

HMOS II allows the production of the 2115H/2125H families, fully compatible with the 1K Bipolar RAMs yet offering substantial reductions in power dissipation. The power dissipations of 525mWmaximum and 656mW maximum compared to 814mW maximum offer reductions of 19% and 36% respectively.

The devices are directly TTL compatible in all respects: inputs, outputs, and a single +5V supply. A separate select (CS)' lead allows easy selection of an individual package when outputs are OR-tied.

PIN CONFIGURATION LOGIC SYMBOL

Cs DIN WE

cs Vco 's

,.

Ao

Ao DON A,

A, WE A,

A,

A,

.,

A,

A, AS A,

"

^{A, A,} A, ¹⁰

"

DOUT A, As 12

GND

.,

^{A, 13}

Vee ^{PIN 16} GNO = PIN B ^.DOUT

PIN NAMES

CHIP5ELECT Ao TOA ADDRESS INPUTS WE WRITE ENABLE

"'.

DATA INPUT

0,,", DATA OUTPUT

1-10

BLOCK DIAGRAM

WORD ]2)( 3(

DRIVER

A[)[)R,<;S OfCODf H

INPUTS CS WE D!N H X X t l l l l H l ^H X

ADDRESS meODER

A" AI> AI A~ A"

(9)~~@~!)@

CONTROL LOGIC ISEE TRUTH

TABLEI

CS WE DIN

~4 '~SI

TRUTH TABLE

OUTPUT OUTPUT

MODE 2115H FAMIL Y 212SH FAMll Y

0,,", 0,,",

HIGH Z HIGH Z NOT SElEctE HIGH Z HIGH Z WRITE "0" \ HIGH Z HIGH Z WRITE ",",

0,,", 0,,", ^READ

2115H/2125H FAMILY ABSOLUTE MAXIMUM RATINGS·

Temperature Under Bias • • • • . . • • . • . • • _1O°C to +B5°C Storage Temperature • • . . • • . • • • . • • • -:-65°C to +l50°C All Output or Supply Voltages . • . . • . • • . . -0.5V to +7V All Input Voltages . . . • . ',' • . . . • . • • . . -1.5V to

+

7V D.C. Output Current . . • • • . • • • • • . • . • . • • • . • 20 mA

D.C. CHARACTERISTICS

[1.2J Vee = 5V ±5%, T A = O°c to 75°C

Symbol T ... Min.

VOl. 2115H125H Family Output Low Voltage

V,H Input High Voltage 2.1

V,L Input Low Voltage I,L Input Low Current I'H Input High Current

1,IcEXI 2115H Family Output Leakage Current . IloF.1 2125H Famliy Output Current (High Z)

los 2125H Family Current Short Circuit to Ground

VOH Family Output High Voltage 2.4

Power Supply Current:

Icc,: 2125H-l

Icc 2115H-212125H-2

1=: 2115H-412125H-4 Ices: 2115H-312125H-3

NOTES:

'COMMENT: Stresses above those listed under "'Absolute Maxi·

mum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability •

Typ. Mu. "UnH CondHlona

0.45 V 101.

=

16mA V

0.8 V

-0.1 -40 IlA Vee

=

Max., V,N

=

0.4V 0.1 40 IlA V""

=

^{Max., V,N}

=

^4.5V

0.1 100 IlA Vee

=

^{Max., VOUT}

=

^4.5V

0.1 50 IlA Vee

=

Max., VOUT

=

^O,5V/2.4V

125 200 mA Vee

=

Max.

V IOH

=

^{-5.2 mA}

80 150 mA

125 - mA All Inputs Grounded, Output

80 Open

80 100 mA

,. The operating ambient temperature ranges are guaranteed with transverse air Ilow exceeding 400 linear leet per minute.

2. Typical limits are at Vee

=

5V. T.

=

+25'C, and maximum loading,

2115H/2125H FAMILY 2115H FAMILY A.C. CHARACTERISTICS

READ CYCLE

2115H-2 Limits

Symbol Test Min. Max.

tACS Chip Select Time 15

tReS [1J Chip Select Recovery Time 20

tM Address Access Time 25

tOH [1J Previous Read Data Valid After Change of Address 0

WRITE CYCLE

Symbol Test Min. Max.

tws [1J Write Enable Time 15

tWR Write Recovery Time 0 15

tw Write Pulse Width 20

tWSD Data Set-Up Time Prior to Wri.te 0

tWHD Data Hold Time After Write 0

tWSA Address Set-Up Time ^. 5

tWHA Address Hold Time 0

twscs Chip Select Set-Up Time 5

tWHCS Chip Select Hold Time 0

[1 J These specifications are guaranteed by design and not production tested.

A.C. TEST CONDITIONS

Vee

2115H

"oUT-~.----4 60DS!

30m!

lOp' (INCLUDING SCOPE AND JIG)

Vee

2115H

"oUT-~r---~

...L.

LOAD FOR tRCS' tws ":"

300~!

5pF

2115H-3 Limits Min. Max.

20 20 30 0

Min. Max.

20

0 20

20 0 0 5 0 5 5

All INPUT PULSES

READ CYCLE WRITE CYCLE

AOA9 _ _ _ _

~~

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _

! - tAA _ -Jf--

Do. -jf-

DATA VALID

PROPAGATION DELAY FROM CHIP SELECT

I-=t= _I-t:j

- twscs

-r-

^tws

wi

"oUT

...

_DATA

I

UNDEFINED

(All ABOVE MEASUREMENTS REFERENCED TO 1,SVI

1-12

2115H·4 Limits Min. Max. Units

20 ns

20 ns

35 ns

0 ns

Min. Max. Units

20 ns

0 20 ns

25 ns

0 ns

0 ns

5 ns

0 ns

5 nS

5 ns

c--

-jf-

'{-

' -

_ 'WHO

_ I W H A _

~~~HCS~

~

2115H/2125H FAMILY 2125H FAMILY A.C. CHARACTERiStiCS

READ CYCLE

Vee = 5V ±5%, TA =

o°c

to 75°C

2125H·1 limit. 2125H· 2 limit. 2125H·3 Limits 2125H·4 Limit.

Symbol Test Min. Max. Min. Max. Min. Max. Min. Max. Units

tACS Ch ip Select Tinie 15 15 20 20 ns

t ZRCS ^[1J Chip Select to HIGH Z 20 20 20 20 ns

tAA Address Access Time 20 25 30 35 ns

Previous Read Data Valid After

-

0 0 0 0

tOH ^[1J ns

Change of Address WRITE CYCLE

Symbol Test Min. Max. Min. Max. Min. Max. Min. Max. Units

tzws [1J Write Enable to HIGH Z 15 15 20 20 ns

tWR Write Recovery Time 0 15 0 15 0 20 0 20 ns

tw Write Pulse Width 15 20 20 25

-

ns

-. -

tWSD Data Set·Up Time Prior to Write 0 0 0 0 ns

tWHD Data Hold Time After Write 0 0 0 0 ns

. -

tWSA Address Set·Up Time 5 5 5 5 ns

tWHA [1J Address Hold Time 0 0 0 0

. -

ns

...

-

twses Chip Select Set·Up Time 5 5 5 5 ns

tWHeS Chip Select Hold Time 0 0 5 5 ns

[1J These specifications are guaranteed by deSign and not production tested.

..

A.C. TEST CONDITIONS

ALL INPUT PULSES

Vee

---r---- ---

^----90%

3.0V p-p I I

5l0E _+..:_;;;_~

_ : ____________

~

_

~-.;;-...:';;;o%~--

( I I I

2125H

Dour ---..---4

300n

READ CYCLE

JOpF (INCLUDING SCOPE AND JIG)

AO.A. _ _ _

j~I..

_ _ _ _ _ _ _ _ _ _ _ _ _ _

1---tAA

Dour DATA VALID

PROPAGATION DELAY FROM CHIP SELECT

t I I I

GND "=' --...: : _ 5ns - : l -^5ns

WRITE CYCLE cs

-J(-

WE

_ t W H O

____ IWHA _

_ I W S C S _

(ALL ABOVE MEASUREMENTS REFERENCED TO 1 !)Vl

2115H/2125H FAMILY 2125H FAMILY WRITE ENABLE TO HIGH Z DELAY

2125H FAMILY PROPAGATION DELAY FROM CHIP SELECT TO HIGH Z

cs

CHIP SELECT

DouT

---"1

DATA OUTPUT --';"';;';';';;';""'-.J[

"'" LEVEL

DouT --"';";;;;';';;';;"'-....,.,J-...,..,-} O.5V

DATA OUTPUT _~ _ _ _!!~~

lALL tzxxx PARAMETER$.ARE MEASURED AT A DELTA Of O.5V FROM THE LOGIC LEVEL AND USING LOAD 1.1

2115H/2125H FAMILY CAPACITANCE*

Vcc=SV, f= 1 MHz, TA =2SoC 211SH Family 212SH Family

SYMBOL TEST LIMITS LIMITS UNITS

TYP. MAX. TYP. MAX.

C1 Input Capacitance 3 S 3 S pF

Co Output Capacitance S 8 S 8 pF

-This parameter is periodically sampled and is not 100% tested.

1-14

TEST CONDITIONS

All Inputs

=

OV, Output Open

cs

= SV, All Other Inputs

=

OV, OutputOjlen

inter

2118 FAMILY

16,384

_{. . '.:}

x 1 BIT DYNAMIC RAM

_.

Maximum Access Thne(ns) Read, Write Cycle (ns) Read-Modlfy-Wrlte Cycle (ns)

• Single +5V Supply, ±10% Tolerance

• HMOS Technology

• Low Power: 150 mW Max. Operating 11 mW Max. Standby

• Low Voo Current Transients

• All Inputs, Including Clocks, TTL Compatible ..

2118·10 2118·12 2118-15

100 235 285

120 150

270 320

320 410

• CAS Controlled Output Is Three-State, TTL Compatible

• RAS Only Refresh

• 128 Refresh Cycles Required Every 2ms

• Page Mode and Hidden Refresh Capability

• Allows Negative Overshoot VIL min = -2V

The Intel@ 2118 is a 16,384 word by 1-bit Dynamic MOS RAM designed to operate from asingle+5V power supply. The 2118 is fabricated using HMOS - a production proven process for high performance, high reliability, and high storage density.

The 2118 uses a single fr'ansistor dynamic storage cell and advanced dynamic circuitry to achieve high speed with low power dissipation. The circuit design minimizes the current transients typical of dynamic RAM operation. These low current transients contribute to the high noise immunity of the 2118 in a system environment.

Multiplexing the 14 address bits into the 7 address input pins allows the 2118 to be packaged in the industry standard 16-pin DIP. The two 7-bit address words are latched into the 2118by the two TTL clocks, Row Address Strobe (RAS) and Column Address Strobe (CAS). Non-critical timing requirements for RAS and CAS allow use ofthe address multiplexing technique while maintaining high performance.

The 2118 three-state output is controlled by CAS, independent of RAS. After a valid read or read-modify-write cycle, data is latched on the output by holding CAS low. The data out pin is returned to the high impedance state by returning CAS to a high state. The 2118 hidden refresh feature allows CAS to be held low to maintain latched data while RAS is used to execute RAS-only refresh cycles.

The single transistor storage cell requires refreshing for data retention. Refreshing is accomplished by performing

Ms-

only refresh cycles, hidden refresh cycles, or normal read or write cycles on the 128 address combinations of Ao through As during a 2ms period. A write cycle will refresh stored data on all bits of the selected row except the bit which is addressed.

PIN

CONFIGURATION LOGIC SYMBOL

AO A, A,

D,.

A, A.

A5 DOUT II,;

RAS CAS WE

Ao-As ADDRESS INPUTS CAS COLUMN ADDRESS STROBE

D,.

DATA IN Dour DATA OUT WE WAITE ENABLE RAS ROW ADDRESS STROBE VDD POWER !+5V) Vss GROUND

BLOCK DIAGRAM

64 x 128 CELL MEMORV ARRAY

_Voo _Vss

DoUT