82S321 SOns Max
0.02 mW/Blt TYpically
• lWo Chip Select Inputs for Easy Memor!, Expansion
• Polycrystalline Silicon Fuses for Higher Fuse Reliability/Higher Programmability
The Intel 82S321/82HS321 are high-performance 32,768-bit PROMs organized as 4096 words by 8 bits. The worst case access time of 40 ns is specified over the DoC to 75°C temperature range. There are two chip selects provided to facilitate expansion into larger PROM arrays. The PROMs use the Schottky clamped TTL technology with polycrystalline silicon fuses. All outputs are initially high and logic low levels can be electrically program-med in selected bit locations.
The 82S321/82HS321 allows present 4K, 8K and 16K PROM users to increase density significantly without sacrificing performance. Intel's 82S321/82HS321 are packaged in hermetic 24-pin dual in-line packages. These 32,768-bit PROMs use the most advanced technology available. As a result, the 82S321/82HS321 combine more high performance, high density and lower power per bit than previous Bipolar PROM designs.
DATA OUT 1 DATA OUT 8
CS, 0,
cs, 0,
A, 03
A, 0,
A, Os
A3 0,
A. 0,
As 0,
A, A, PIN NAMES
As
Ao-A'1 ADDRESS INPUTS A,
CS"CS2 CHIP SELECT INPUTS") A"
An
O,-Oe DATA OUTPUTS
(1) To select the PROM C'S, V,L and CS2 '" V,H
Figure 1. Block Diagram Figure 2. Pin Configuration Figure 3. Logic Symbol
Intel Corporation A . . umea No R •• poneibilty for the U . . of Any Circuitry Other Than Circuitry Embodied in an Intel Product. No Other Circuit Patent License • .,.Implied.
82S321/82HS321
PROGRAMMING
The programming specifications are described in the PROM programming section of the Intel Data Catalog.
This algorithm is precisely the same as that used to program all other Intel Bipolar PROMs.
ABSOLUTE MAXIMUM RATINGS·
Temperature Under Bias ... -65'C to +125'C Storage Temperature ... -65'C to +16O"C Output or Supply Voltages ... -0.5V to 7 Volts All Input Voltages ... -1.5V to 5.5V Output Currents ... ; ... ; .... ".100 rnA
"NOTICE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional opera-tion of the device at these or any other condiopera-tions above those indicated in the operational sections of this specifi-cation is not implied.
D.C. CHARACTERISTICS
(All Limits Apply for Vee = +5.0V ± 5%, TA = O'Cto +75'C)Symbol Parameter Umlts
Test Conditions Min. Typ.[11 Max. Unit
IFA Address Input Load Current -0.05 -0.25 rnA Vee = 5.25V, VA .; 0.45V IFS Chip Select Input Load Current -0.05 -0.25 rnA Vee = 5.25V, Vs = 0.45V
IRA Address Input Leakage Current 40 /LA Vee =5.25V, VA = 5;5V
IRS Chip Select Input Leakage Current 40 /LA Vee = 5.25V, Vs = 5.5V 1101 Output Leakage for High Impedance State 40 /LA Vo = 5.5V or 0.5V,
Vee = 5.25V, CS1 = 2.4V Ise[21 Output Short Circuit Current -15 -40 -100 rnA Vo = OV
VeA Address Input Clamp Voltage -0.9 -1.5 V Vee = 4.75V, IA = -10 mA Ves Chip Select Input Clamp Voltage -0.9 -1.5 V Vee = 4.75V, Is = -10 rnA
VOH Output High Voltage 2.4 3.2 V 10H = -2.4 rnA, Vee = 4.5V
VOL Output Low Voltage 0.3 0.45 V Vee = 4.75, 10L = 10 rnA
lee Power Supply Current 130 175 rnA Vee = 5.25V
VIL Input "Low" Voltage 0.85 V Vee = 5.0V ± 5%
VIH Input "High" Voltage 2.0 V Vee = 5.0V ± 5%
NOTES:
1. Typical values are for TA = 25'e and nominal supply voltages.
2. Unmeasured outputs are open during this test.
CAPACITANCE(3)
(TA=
25'C, f=
1 MHz)Symbol Parameter
Typ.
Limits
Max. Unit Test Conditions
CINA Address Input Capacitance 4 10 pF Vee = 5V VIN = 2.5V
CINS Chip-Select Input Capacitance 6 10 pF Vee = 5V VIN = 2.5V
GoUT Output Capacitance 7 12 pF Vee = 5V VOUT = 2.5V
NOTE:
3. This parameter Is only periodically sampled and is not 100% tested.
2-66 AFN'()20e6A
inter 82S321/82HS321
A.C. CHARACTERISTICS (Vee
=
+5V ± 5%, TA=
ooe to + 75°C)Symbol Parameter
tA Address to Output Delay tEN Output Enable Time tOlS Output Disable Time
SWITCHING CHARACTERISTICS Conditions of Test:
Input pulse amplitudes: 2.5V
Input pulse rise and fall times of 5 nanoseconds between 1 volt and 2 volts
Speed measurements are made at 1.5 volt levels Output loading is 10 mA and 30 pF
Frequency of test: 2.5 MHz
WAVEFORMS
ADDRESS TO OUTPUT DELAY
ADDRESS INPUT
OUTPUT
OUTPUT
---JI~
__________
- JI,
I,
Max. Limits
Unit Test Conditions 82S321 82HS321
50 40 ns CS1 = VIL and
35 30 ns eS2 = V1H to
35 30 select the PROM.
ns
10 mA TEST LOAD Vee
~470"
- ~'K"
CHIP SELECT TO OUTPUT DELAY
~,---~ r---~
~ ______ ~I~ __________ - J OUTPUT
lEN
Bipolar PROM Programming
1. A 5mA current must be forced into the output to be programmed by a current source. The current source must be clamped to Vee by a silicon diode. All the other inputs must be floating until it is their turn for programming. The Vee power supply and the chip select (CS) input is pulsed as shown in Figures 1 and 2. The width of Vee is linearly increased from 0.2"s to 8"s according to the ramp time shown in Figure 3. The total ramp time for a group of fo.ur outp.uts is 180ms for a group of eight outputs.
The Vee program pulses are multiplexed during a cycle time to the outputs of the. word to be programmed. The cycle time (teyel between the Vee program pulses to the same .output will increase as the Vec program pulse width increases from 0.2"s to 8"s.The time (t D) between Vee pulses oftwo different outputs is constant at 1.8"s.
2. All outputs must be continuously monitored for programming verification. This verification rnust occur after Vcc has been at 4.5V for 90% of tD and prior to Vec rising to 12.5V.The program/verification cycles ml.lst still be applied (with the pulse width still linearly increasing to II maximum of 8"s) eventhouQh the output has been sensed as being programmed. An additional 128 verifications (i.e., 128 program/verify cycles) on eac.h output must be obtained to insure a correctly programmed output. This additional 128 verification is a minimum number and must occur after all the bits of the word are sensed as being programmed. PI~ase refer to Figure 1 for the timing waveforms.
More than 128 program/verify cycles may be required to achieve the 128 verifications on each bit. The cycles should still continue even if one bit fails, since the verifications are not required to be in consecutive sequence. After the 128 verifications have occurred for all bits, a final Vcc and CS pulse at a width of 2.5ms is simultaneously applied to all outputs that are being programmed. Programming snould cease if the 128 verifications are not aChieved in800ms.
3. A 4mA ± 50% Ics current must also be forced into an appropriate chip select. les is forced into CS4 (pin 18) of 3604A/3624A, CS2(pin 10) of 3625A, CS3 (pin 19) of 3628, and CS2 (pin 19) of 3636. The 4mA current into the chip select input may be easily accomplished by using a 1.2K resistor connected to a ± 15V power supply, The voltage on the chip select input will be approximately 10V with the 1.2K resistor.
4. The Icc source used for programming should be able to supply 600mA during V1H . Table V. Programming Characteristics
TA = 25°C
Symbol Parameter
VIH1 Vee Program Pulse Amplitude V 1H2 CS Program Pulse Amplitude Programming Instruction 3 -for Details)
Max. Units Conditions
13 V 1.2K resistor from a 15V power supply
\
I
'" •
. - - - · C Y C ISEE FIG. 2 FOR DETAILS)L 128tCVC
r----INOTE21
-I-
,~v~'::::~JUULJUUL~JL
·,ov n n
OUTPUT 1 ""BV --I I ... ----~n
.... ---...J L,
o .•• V IMAXI II
[PROGRAMMED 0 (NOTE 1)
'"'lOV
r1 r1 ~ .JL
OUTPUT. ·.V - - - , ~:,.l---'
~:~l---O.46V (MAXI 1 l
PROGRAMMEQ 0 INOTE 11
OUTPUTN
·:::---lZ~L...---zl;~ ) n I I
D.46VIMAXI
t~ ~~ L
1Z.5V Vee
C.sv
~3V
Ci ov
LpROGRAMMED 0 (NOTE 11
Figute 1. Programming Cycles.
NOTES: 1. ~~~;:~~::~~~~~~~~u~~::~~~~:~~Els ~~8~~N~~~O~T~:~ ~~~N~~ ~~~~ AND PRIOR TO Vee RISING TO 12.SV.
2. AFTER THE LAST BIT HAS BEEN PROGRAMMED. 128 ADDITIONAL VERIFICATIONS ARE REQUIRED FOR EACH OUTPUT TO BE CORRECTL V PROGRAMMED.
3. AFTER THE 128 PROGRAM VERIFICATIONS, A FINAL 2.5
m.
Vee ANDes PULSE SHOULD BE APPLIED WHILE SIMULTANEOUSLY ENABLING THE CURRENT SOURCES TO ALL OUTPUTS WHICH ARE TO BE PROGRAMMED.5V '0
\
SV
/ \..
",'0V
n
OUTPUT 1
I \
·.V ----'
'---l~__::r__---JUNPROGRAMMED BIT
.. 10V
n
OUTPUT 2 / \
.SV ____________________________ .J
~---l~l~---OUTPUT N
·,ov
.SV _________________________________________________J\
... ______________________________ . .Figure 2. Programming Cycle Details.
2-69
(al RAMP TIME IN PROGRAMMINC 8 OUTPUTS
Ib) RAMP TIME IN PROGRAMMING 4 OUTPUTS
02 0.2
'00 200 300 400 500
...
700 800 100 200 .300 400... ...
700 800PROGRAMMING ELAPSED TIME Imll PROGRAMMING ELAPSED TIME Imll
Figure 3.
Vee
Pulse Width VI. Programming Tima.2-70
BIPOLAR PROM FAMILY
Maximum Operating
No. No. Maximum Power Temperature Power
of of Access Dissipation Range Supply
Type Bits Organization Pins Output (ns) (mW) (OC) (V)
3628A·1 8192 1024x8 24 T.S. 50 998
o
to 75 5V±10%3628A·3 8192 1024x8 24 T.S. 70 998
o
to 75 5V±10%3628A·4 8192 1024x8 24 T.S. 90 998
o
to 75 5V±10%3636 16384 2048x8 24 T.S. 80 998
o
to 75 5V±10%3636·1 16384 2048x8 24 T.S. 65 998
o
to 75 5V±10%36368·1 16384 2048x8 24 T.S. 35 998
o
to 75 5V±10%36368·2 16384 2048x8 24 T.S. 45 998
o
to 75 5V±10%M3636 16384 2048x8 24 T.S. 80 998 -50 to 125 5V±5%
BIPOLAR PROM CROSS REFERENCE
Intel Part Number
Part Prefix and Direct For New
Number Manufacturer Organization Replacement Designs
82S181 N·Signetics 1024x8 3628A·3 3628A·1
82S191 N·Signetics 2048x8 3636 36368·1
82S191 S·Signetics 2048x8 M3636