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Pin Compatibility

Dans le document COMPONENT inter (Page 136-142)

The 2816 pinout has been designed for

compatibil-it~ with present and future memory products. The E PROM is a member of Intel's JEDEC standard Byte-Wide memory family which allows density up-grades, functional interchange, and extended prod-uct life. Figure 17 shows this JEDEC 28 pin site pinout approach.

-.n+_f

l l ' e '

281&

AP137-8298 Functional Specification and

... .'

~ ' " c ~ ~

~ ...

Firmware Description

'"

i

Ie

.... .... ....

'" '"

'"

'" '"

'" AP138-A 2716 to 2816 Programming Socket

v •• Vee Adapter

A" PGM

A, A, A, A, Vee Vee. Vee Ne To obtain this literature contact your local Field

Sales office. In addition, your Field Applications

A, A, A, A,

Engineer can d'iscuss with you the controller

inter-A. A. A, A. faces for different MPU system configurations.

v •• A" V •• A"

DE OElVpp OE liE All of the above literature will be available at the end

A10 A" AIO AIO of Q2 1981. The E2PROM Applications Handbook is

CE CE CE CE available now.

Figure 17. JEDEC 28 Pin Site Byte-Wide Standby Mode Philosophy

Available, Literature

To, give the system designer an opportunity to more thoroughly understand the device attributes and uses, a library of E2 information is available in the E2 Applications Handbook Volume II. It includes these application notes:

'AP100-Reliability Aspects of a Floating Gate

" 'E2PROM

AP-101-The 2816 Electrical Description AP-102-2816 Microprocessor Interface

Considerations

AP-103-Programming E2PROM with a,Single 5-Volt Power Supply

AP-107-Hardware and Software Download Techniques with 2816

AP135-8298 Integrated E2 Controller AP136-A Multibus-Compatible 2816 E2PROM

Memory Board

For footnotes see page 13,

The 2816 has a standby mode which reduces active power dissipation by 55% from 11 0 rnA to 50 rnA. The 2816 is placed in the standby mode by applying a TTL high signal to the CE input. When in the standby mode, the outputs are in a high impedance state, independent of the OE input.

Output OR-TIEING

Because 2816s are usually used in larger memory arrays, Intel has provided a 2-line control function that accommodates this use of multiple memory connections. The 2-line control function allows low power dissipation (by deselecting unused devices), and the removal of bus contention from the system environment.

To most effectively use these two control lines, it is ,recommended that CE (pin 18) be decoded from addresses as the primary device selection function.

OE (pin 20) should be made a common connection to all devices in system, and connecled to the RD line from the system control bus. This assures that all deselected memory devices are in their low power standby'mode and that the output pins'are only a,ctive when data is desired from a particular memory device.

2-44 AfN.01635B

inter 2816

ABSOLUTE MAXIMUM RATINGS·

Temperature Under Bias ... -10°C to +80°C Storage Temperature ... -65°C to +100°C All Input or Output Voltages with

Respect to Ground ... +6V to -0.3V VppSupply Voltage with Respect to

Ground During Write/Erase ... +22.5V to -O.W Maximum Duration of Vpp Supply at 22V

During E/W Inhibit ... 24 Hrs.

Maximum Duration of Vpp Supply at 22V

During Write/Erase ... 70 ms[81

'NOTICE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ILl Input Leakage Current ILO Output Leakage Current ICC2 VCC Current (Active) ICCl VCC Current (Standby) IpP(R) Vpp Current (Read) VIL(D.C.) Input Low Voltage (D.C.) VIH Input High Voltage VOL Output Low Voltage VOH Output High Voltage·

Vpp Read Voltage

VldA.C.) Input Low Voltage (A.C.)

WRITE

Symbol Parameter

Vpp Write/Erase Voltage

Ipp(W) Vpp Current (Byte Erase/Write) VOE OE Voltage (Chip Erase) Ipp(l) Vpp Current Inhibit Ipp(C) Vp p Current (Chip Erase) For footnotes see page 13.

2816

Typ.ll] Units Test Conditions

Max.

Typ.ll] Units Test Conditions

Max.

inter

CAPACITANCE[1] TA = 25°C,f = 1 MHz Symbol Parameter

CIN Input Capacitance CaUT Output Capacitance

Cv

cc Vcc Capacitance

Cv

pp Vpp Capacitance

A.C. CHARACTERISTICS Output Load: 1TIL gate and

CL = 100 pF Input Pulse Levels: 0.45 to 2.4V Timing Measurement Reference tACC Address to Output

200 250 300 350 400 450 ns CE = OE =VIL tOF Output Enable High

0 80 0 100 0 130 ns CE = VIL

Symbol Parameter Typ;[1) Units Test Conditions

Min. Max.

For footnotes see page 13.

2-46 AfN.01635B

inter

2816

WAVEFORMS

READ

I r - - - -

- - - ' \ I

ADDRESSES ADDRESSES VALID

1"-_ _ _ _ _ _ - - - _ _ _ -JI

I ' - - - - t - - - ' I

/

OE _______ -JI

/

OUTPUT---+---~K

BYTE ERASE OR WRITE1S1

ADDRESSES

} K

4 - -Ics ----.

...

IpRC 14) twR ....

--\ /

4 - - -lAS - - - . .

-

IWp~1 . . . IWR ....

---+-tpFT

-(4-.V)

Vpp

1 \

'05-"

- -

4-tOH

DATA IN VALID

'BOS_

I- ...

--'BOH

For footnotes see page 13.

2816

WAVEFORMS (Continued)

CHIP ERASEI6]

ce---""""'\

v p p - - - -_ _ _ _ _ _ --{

(_-IV)

DATA IN

---JI

OE _____ ~V~IH _ _ _ ~

NOTES:

1. This parameter is only sampled and not 100% tested.

2. OE may be delayed up to 230 ns after falling edge of CE without impact on tACC for 2816.

3. tOF is specified from OE or CE whichever occurs first.

4. The rising edge of Vpp must follow an exponential waveform.

That waveform'S time constant is specified as tpRC. See Intel's AP-102 for details.

5. Prior to a data write, an erase operation must be performed.

For erase, data in = VIH.

6. In the chip erase mode DIN = VIH.

2-48

tOH

7. To allow immediate read verify capability, Vpp can be driven low in less than 50 ns. See AP-101 for more information.

8. Adherence to TWP specification is important to device reliability.

9. To prevent spurious device erasure or write, VCC must be applied simultaneously or before 21 volt application of Vpp.

Vpp cannot be driven to 21 volts without previously applying VCC·

10. The data in set up and hold times for chip erase are identical to those specified for byte erase.

11. This switch includes automatic voltage shutdown on power fail.

AFN-D1635B

2817

Dans le document COMPONENT inter (Page 136-142)

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