VHF GENERATOR MODEL 73OA

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MAINTENANCE HANDBOOK

PART ONE

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C O N T E N T

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CHAPTER VI MAINTENANCE VI-1

- Continuous FM board 0107308301-1

1

-ⁱ - 10 000 Steps board _0274750000-1

- ²⁰⁰ Steps board 0274760000

-

¹

- Phase-lock Oscillator 0274770000

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- ² MHz Steps board _0274780000

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- Modulations _0274800000

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Analog board 0274810000

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400 MHz Generation board 0274990000

-

¹

-

^{VHF Module} _0275200000

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- Attenuator Assembly 0275710000

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- ⁴⁸⁰ MHz Generation Module 0276450000

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CHAPTER VI

1

MAINTENANCE

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FAULT FLOWCHARTS

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Fault flowcharts have been established for e a c h i n s t r u m ent function showing t he f a u l t s m o s t likely t o o c c u r in o r d e r t o f a cilitate t h e repair of the i n s t r u m e n t.

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They indicate the c h e c k s t o b e m ade and localize f a u l t s t o t h e s u s p e c t module, s ub

-

a s s e m b l y or c o n n e c t i o n.

1) F a u lts a f f e c t i n g t h e display,

F a u l t s affecting R F frequency,

F a u l t s affecting R F o u t p u t amplitude, F a u l t s a f f ecting AM modulation

,

F a u l t s a f f e c t i n g FM and

0

M modulations.

2) 3)

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i n d i c a t o r l i t

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mains c o r d Are t h e mains no

p r e s e n t ? ^&

r— y e s

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Replace fuse I s t h e f u s e no

s o u n d ? *

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STANDBY i n d i- c a t o r ^{l i t .}

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^{No CLOCK}

^ i n d i c a t o r ^master

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i n d i c a t o r See CPU b o a r d

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F a u l t a f f e c t i n g m o d u l a t i o n

F a u l t i n a n a l o- g i c a l b o a r d I N I XT s w i t c h o r LF

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y e s y e s

F a u l t i n e x t e r n a l

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c o n t r o l P o o r

c a l i b r a t i o n

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F a u l t i n

0M b o a r d r a n g e s w i t c h i n g O s c i l l o

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c h e c k

o n t e r m i n a l 6 a n a l o g i c a l b o a r d

c o n n e c t o r

No y e s y e s

LF P r e s e n t d e v i a t i o n

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O s c i l l o

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c h e c k o n t e r m i n a l 19 a n a l o g i c a l b o a r d

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F a u l t i n a n a l o g i c a l

b o a r d

r y e s

LF P r e s e n t

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n o

F a u l t i n a n a- l o g i c a l b o a r d gene LF I N T 1kHz

t o 400 Hz Check LF a m p l i t u-

de a t t e r m i n a l 1^c a n a l o g i c a l b o a r d

c o n n e c t o r

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P o o r d e v i a t i o n

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n o yes

F a u l t o n a n a l o g i c a l

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Check 8 0 MHz o u t p u t o n M o d u l a t i o n

b o a r d

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s y n c h r o n i s

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Out o f

s y n c h r o n i s

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F a u l t i n 400 MHz g e n e r a t o r n o

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CONTINUOUS FM BOARD ariretE0i®Efcrran^]C2gyi!t

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CONTINUOUS FM BOARD

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This board g e n e r a t e s a n 80 MHz FM frequency with bandwidth ranging from continuous t o ± ^{1 0 kHz} of Fo

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It is substituted for a n 80 MHz nonmodulated or AM signal^, o r for a n 8 0 MHz FM o r

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^{M signal}

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Description

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An 8 MHz q u a r t z oscillator is f requency-modulated by a voltage applied o n varicap BB 809 which modifies t h e c apacity of t h e q u a r t z oscillating circuit.

T h e signal is linearized by t w o operational amplifiers, A2 and A 3, and a t y p e AD534JH linearizing circuit which c o m p e n s a t e s for t h e varicap fault in linearity.

Amplifier A2 c o r r e c t s t h e t e r m in X2 by P2.

I t s gain is a d j u s t a b l e from + 1 t o

-

^1.

Amplifier A3 c o r r e c t s t h e t e r m in X3 by P3

.

I t s gain is a d j u s table from + 4 t o

-

^4.

T h e A3 o u t p u t drives t h e c u r r e n t of one of t h e sections of a c u r r e n t block made up of t r ansistors BC416 and BC414, designed t o apply t h e corrective

t e r m s t o a m p l i f i e r A 4 and shift t h e _continuous audio-frequency signal ; this may take place with a c o r r e ction cell link, if applicable.

Regulation of f r e q u e ncy deviation takes p l a c e on the _modulation audio- frequency i n p u t by variation in t h e g a i n of a m p l i f ier A l, which may be a djusted by P I ( 10 V DC maximum)

.

This amplified audio-f r e quency signal i s then a pplied t o t h e linearizing circuit a n d shifting amplifier A4.

T h e role of a m p l i fier A4 is t o c e n t e r t h e modulation audio-frequency signal around 6 V DC ( adjusted by P4 on the c u r r e n t block ) in order t o use t h e m o s t linear p o r t i on of the varicap slope

.

The o u t p u t of a m plifier A4 a p plies t h e audio

-

frequency signal t o t h e varicap by means of a s e r i e s RL n e twork which drives it under low impedance in order t o l i m i t a u d io

-

f r e q u e n c y signal noise while remaining a t high impedance under 8 MHz.

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The 8 MHz q u a r t z oscillator, which is thermostatically controlled in order t o

limit t e m p e r a t u r e drift

,

is multiplied by t w o (diode doubler⁾ and _{applied t o} a c l ass C a m p lifier in the collector ; a circuit in t h e collector tuned on harmonic 5 enables 8 0 MHz selection

.

This 8 0 MHz signal i s s e n t across ^a PIN diode switch after filtering which selects e i t h er it o r t h e signal o u t p u t by the Modulations board

-

^{or + polari}

-

zation of the d i o d e s by means of S N4

.

^{When the} 8 0 MHz signal from the Modulations board i s selected, t h e 8 MHz oscillator is c u t off by non- conduction of Q5. T h e level of the 80 MHz signal i s regulated by adjusting P5 on the class C amplifier

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No FM Modulation

Check 80 MHz oscillator

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10 000 STEPS BOARD adret litadfcrorainpm

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The

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^{10 000}

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^{Steps board generates} the increments from 1 Hz to 9.999 kHz,

or 9999 steps. Frequency resolution of the 730 is 1 Hz.

An 80 to 120 MHz oscillator drives^,two separators

.

Q3 sends the signal to the 400 to 600 kHz output across a divider by 200 (4 x 10 x 5 ) ; Q4 is used as an ECL - TTL adapter

.

Additionally, Q3 transmits the signal to the 20,000 to 29,999 programmed divider

.

Phase-lock oscillator on the CPF SN07 is brought about by comparison between the output of this divider and a 4 kHz reference frequency.

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This latter is obtained from the input 10 MHz signal after division by 2500 ( lO ^'x 5 x 50)

.

^Q09 is a TTL - ^MOS - ^{15 V} adapter.

The programmed divider first uses an ECL SP 8647 circuit which divides hy 10 or 11

,

followed by divider by 2 or 3 SN10, then three dividers by 10 in series

,

SN13, SM16 and SN18. Division ratio coding is sent to the 74LS85 comparators

,

SN12

,

SN15 and SN17

,

by means of registers SN19 and SN14..

These receive signals from the data bus and are addressed by SN 21 to which is connected the address bus ; validation of this decoder is ensured by bit E

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Operation

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The

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or

199 steps

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^{To this}

,

it adds the increment made on the

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^{10 000}" ^Steps board

,

or 9.999 kHz maximum

.

^It features two oscillators

.

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The first oscillator, covering the 79.6 to 119.4 MHz range, has^- its own independent phase-loop

.

Its frequency, after division by 398 to 597 in a programmed counter

,

is compared to a 200 kHz reference in CPF SN 7

.

^The

downstream current block delivers the oscillator phase-locking voltage

,

which is also used for approach of the 80 to 120 MHz oscillator by means of follower amplifier SN6.

The second

,

80 to 120 MHz oscillator represents the sum of the 400 to

600 kHz frequency output from the

"

^{10 000}

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Steps board and the 79.6 to

119.4 MHz oscillator

.

^The difference in frequency between the two oscil

-

lators

,

made in the diodes mixer

,

is compared in CPF SN5 to the 400 to

600 kHz frequency output from the

"

^{10 000}

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Steps board

.

The CPF output locks the 80 to 120 MHz oscillator across integrator amplifier SN2

.

Circuit SN 20 is an address decoder

.

It changes the data in register SN13, which represent the instruction of the programmed divider

.

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SYNOPTIQUE

C o u n t e r 398/597

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SN19 SN10

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SN13 SN20

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Signal at PI08

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CA, 01 and 02 Oscillation

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Voltage on L01

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amplifier SN6 Voltage

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See divider and coding Counter

division ratio correct

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See CPF SN7 and current

mirror presence of yes

200 kHz reference

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LOCK OSCILLATOR J

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The Phase

-

lock oscillator board performs the _following :

* approach of the 396

/

574 MHz oscillator, and

* approach of the final 400 to 500 MHz oscillator, as well as frequency tracking of both oscillators.

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A frequency comparison device is activated with each frequency change made on the front panel keyboard and prepositions the 396

/

574 MHz and 400 to 580 MHz oscillators on their new value. This device operates only in a transient manner (approximately 2 ms ).

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The frequency output by the 396

/

⁵⁷⁴ MHz oscillator is divided by 64 in SN18 and by 198 to 297 in the programmed divider controlled by SN15. The frequency is 31.25 kHz at output and is compared in _comparator SN 5 to the reference frequency _obtained after division by 320 in dividers SN8 and SN 4.

The _{comparator operates} constantly but coincidence circuit SN7 triggers monostable SN3 with each new counter data bit ; for approximately 2 ms

,

this monostable closes switch SN1. This switch validates the approach of the 396

/

⁵⁷⁴ MHz oscillator and the 400

/

⁵⁸⁰ MHz oscillator.

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In order to result in _correct tracking between the two oscillators amplifier with adjustable shift, SN19

,

is inserted into the _{output to} the 400

/

⁵⁸⁰ MHz approach ; adjustments are made at 1 and 179 MHz.

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_{2 MHz STEPS BOARD}

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The 2 MHz Steps board performs the following :

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* generation of 90 steps of 2 MHz between 396 MHz and 574 MHz, and

* positioning of the final 400 to 580 MHz oscillator on a multiple of _{2 MHz}, selected in function of frequency coding.

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1 A frequency comparison device continuously checks the equality between the frequency displayed and the frequency of the 396 to 574 MHz oscillator

.

^This

device is made up of a double sampler.

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For the first sampler a comb of five discreet frequencies ( 400, ⁴⁴⁰, ^'480

,

520 and 560 MHz) is generated from _{an 80 MHz} reference signal

.

These five frequencies are automatically selected by a register in function of _output frequency coding and are mixed in Ml with the frequency from the 396 to 574 MHz oscillator in order to always result in an _output multiple of 2 MHz for this latter ⁽which may range up to 10 times 2 MHz )

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The frequency thus generated is then compared in a second sampler

,

M2

,

to

a 2 MHz pulse obtained by dividing the 80 MHz reference signal by 40

.

^{A DC}

voltage is generated on the output of this sampler ; this voltage is propor

-

tional to the phase difference between these two frequencies

,

enabling finely tuned phase-locking of the 396 to 574 MHz oscillator. If a new code change occurs

,

this voltage is. temporarily blocked for 2 ms and a phase

-

^locking

voltage output by the phase-lock oscillator board prepositions the oscillator via R65.

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At the end of this period

,

this voltage is blocked and the

"

^fine" ^phase-loop is switched in

.

The frequency is delivered to the outside of the board by two separator stages

,

Q15 and Q16

,

in order to drive the phase

-

lock oscillator board and the VHF Module

,

and to the outside via Q14 to drive modulator Ml.

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MODULATIONS BOARD

This board generates the modulation functions used in the 730

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In FM and

0

^M modes

,

an 80 MHz oscillator slaved with a low bandwidth is substituted for the 80 MHz master oscillator

.

FM and

0

^{M modulation is}

carried out

_

^{on this} oscillator

.

Operation of the 80 MHz oscillator is enabled by bits FM, FM_{/10 and}$M

,

which additionally ensure inhibition of ⁸⁰ MHz

master oscillator amplifier Al

.

In FM mode, the 80 MHz frequency is divided by 8 in D1 (SNll ) and then by 500 in D2 ( SN12 and SN13) in order to be compared to the 20 kHz reference signal resulting from division of the 10 MHz master oscillator frequency by 500 in D3 ( SN4 and SN6)

.

There is a DC voltage proportional to the variation in 80 MHz oscillator frequency on the output of CPF1 ( SN14 and SN15) and FL1 (1

/

^{2 SN10)}

.

Amplifier A5 (1

/

^{2 SN10)} incorporates the audio-^frequency

signal in the slaving loop and, additionally, enables regulation of gain and sets the phase to 40 Hz

.

Current amplifier A6 slaves the oscillator via switch Cl ( SN8)

,

whose control is linked to the control of CPF1

.

In

0

^{M mode, the 80} MHz frequency is divided by 8 in D1 and by 4 in D4 (SNl) in order to be compared to the 2.5 MHz reference signal resulting from division of the 10 MHz master oscillator frequency by 4 ( SN3)

.

There is a DG voltage proportional to the variation in 80 MHz oscillator phase on the output of Ml and FL2

.

^{Amplifier A}8 (SN5) incorporates the audio

-

^frequency

signal into the slaving loop and, additionally, enables regulation of

0

^{M gain}

.

Semi-integrator amplifier A7 enables oscillator slaving via switch Cl.

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In AM mode, dividers D2

,

D4 and D5 are blocked

,

as well as CPF1 and 01

.

Mode switch CM1 ( SN16 and SNl7) switches the audio-frequency signal to

amplifier A6 (1

/

^{2 SN}19) which

from this amplifier a comparison circuit continuously compares the audio- frequency signal with a reference voltage and the audio-frequency signal output from a detector located on the "⁴⁰⁰ MHz + 80 MHz'¹ board

.

The result of this comparison modulates the transmitter current of modulator M 2 by means of semi-integrator amplifier A9

.

There is an 80 MHz frequency

,

which is amplitude

-

^{modulated to the rythm. of the audio}

-

frequency signal

,

available on the output of M 2

.

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regulation of AM gain

.

Downstream ensures

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MODULATIONS

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A control circuit (SN24 and SN21), which receives this data by a bus from the CPU

,

ensures all of the various board functions and inhibitions in combi

-

nation with the control logic from SN22 _{and SN}23.

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Finally, in

]

master oscillator signal transits only by amplifier A1 and modulator M 2

.

^The

modulation current from this latter is fixed at a mean value of that existing to have 100% AM

.

In addition

,

input of the 10 MHz reference _signal is blocked in FI

,

which cancels out the 20 kHz frequency _{necessary to} the internal audio-frequency signal. This frequency is thus blocked in external audio-frequency operation.

mode, all modulation functions are blocked

.

The 80 MHz

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8 0 MHz

T o c o n t i n u o u s FM

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g e n e r a t i o n 4 0 0 MHz + 8 0 MHz

CW o r AM ^\

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c o n t r o l FM o r

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A2 SYNOPTIQUE

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8 0 MHz FM o r

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