Micro Technologry SSM

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SolidStcte

Micro Technologry SSM

2r00

for Music

SSM 21OO MONOLITHIC LOG/ANTILOG AMPLIFIER

D E S C R I P T I O N

The SSM 2100 is a complete monoi:thic subsystem for the realization of logarithmic and exponential transfer characteristics.

Included are two precision op-amps, a high conformance transistor pair and a precision bandgap voltage reference.

Additionally, the chip has a substrate temperature regulator which stabilizes the scale factor and greatly attenuates drift ot the reference. A negative reference voltage is also available to facilitate externaltrimming.

FEATURES

I 5 0 0 p A I n p u t B i a s C u r r e n t ( u n t r i m m e d ) I 5 0 p A In p u t B i a s C u r r e n t ( t r i m m e d ) I 4mV Input Offset Voltage

I 1Oppm/"C Reference Drift I 3Oppm/'C Scale Factor Drift a 0.25"/"Conformance

I 3 Decade Dynamic Range (Voltage Input) I 5 D e c a d e D y n a m i c R a n g e ( C u r r e n t I n p u t )

A P P L I C A T I O N S

I P h o t o d i o d e P r e a m p l i f i e r I Absorotion Measurement I Log Sweep Generators

I High Resolution Data Acquisition I Analog Computation Circuits I Analog Compression/Expansion I Linear to dB Conversion

1 2 3 4 5 6 7 B

1 6 t 5 1 4 1 3 1 2

il

1 0 I

I cgvP 'U'

1J 6h

FEEDBACK V

T E M P E R A T I ' B E BEGUTATOR &

B I A S C I R C U I I R Y G N D 1

TEN/P ADJ C O M P

G N D 2 R E F I N

N . C

FEEDBACK CON/P O U T COIVP S I G I N GNt] 3 F E F O I . J T R E F C O M P

PrN OUT (TOP VIEW)

F I G U R E 1 . B L O C K D I A G R A M

Solid State Micro Technology for Music, Inc., 20768 Walsh Avenue, Santa Clara, CA 95050, USA (4081 7 27-0917 Telex 1 71 1 89

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SPECIFICATIONS- OPERATING TEMPERATURE STORAGE TEMPERATURE - 10"C to + 55'C - 55'C to + 125'C

The following specifications apply for V" - * 15V R'urr : 1 .6kO, 5"C < TA < 50"C, l".r : 1mA, unless otherwlse noted.

PABAUETER (SYMBOL) MIN TYP ilAX U N I T S C O N D I T I O N S

Conformity Error (V",.,o,) (Note 1)

0.25 0 . 4

%

o // o

l,* : 100nAto 100pr,A 1 , " : 1 0 n A t o 1 m A (lnput Offset Trimmed) Scale Factor (V,"",") 6s 70 75 mV/Decade Measured at Pin 16 Scale Factor

Temperature Drift

(TC V"",b)

30 ppm/'C

Input Offset Voltage (V,".) (Note 2)

4 8 m V

Input Bias Current (lo) ( N o t e s 1 , 2 )

500 2000 pA

Output Offset Voltage

(v-") ³⁰ ⁷⁰ ^{m V} l , * : l ^ . r : 1 m A

Scale Factor Set at 1V/Decade Power Supply Rejection

Ratio (PSRR) (Note 3)

500 250

pV/V P,V/V

+ 1 2 V < V + < + 1 7 V 1 2 Y . , . V - > - 1 7 V

Scale Factor Set at 1V/Decade Output \,{rltage Swing

(Vort)

- 0.2

1

+ 1 0 + 1 0

V V

R L > 1 0 K Rt=- 2K

Reference Output Voltage

(V*.. + ) ^{4 . 7} ^{5 . 0} 5 . 2 V No Load

Reference Output Voltage Temperature Coefficient

(TC VnEF)

1 0 ppm/'C

Reference Output Current 5 mA

Reference Load Regulation 0 . 0 1 5 "hlmA R L > 1 K o

Reference Supply Rejection 0 . 0 4 7"lY + 1 2 V < V + < + 1 7 V

Voltage at Pin 7 (V"., - ) 6

⁷

B V

Positive Supply Current ( 1 . + )

3 5 2 0 5 0 5

mA m A m A m A

Tn : 25"C To : 50"C To : 5'C

H e a t e r D i s a b l e d Negative Supply Current

( t " - ) ⁵

MA

Heater Start up Current 80 120

MA

Regulated Chip Temperature (T*ro)

53 60 75 .C

Notes

1). Guaranteed by design but not directly measured 2). Applies to both signal and reference inputs.

-Final specifications may be subject to change.

3). Referred to output in log mode, or to input in antilog mode 4). Specifications apply after a 50 second warmup period.

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Princlple of Operation

The 2100 uses the predictable logarithmic relationship between the collector currents and differential input voltage of an NPN transistor pair, given bY:

^v,^,

_{' '}

: !I rn !t

_q

1 " ,

w h e r e k : B o l t z m a n n ' s c o n s t a n t ( 1 . 3 8 x 1 0 ' z 3 J / K ) Q : c h a r g e o n th e e l e c t r o n ( 1 . 6 x 1 0 1 ' g C )

T : a b s o l u t e t e m p e r a t u r e ( K )

T h e a b s o l u t e t e m p e r a t u r e t e r m is e l i m i n a t e d o n t h e 2 1 0 0 b y r e g u l a t i n g t h e c h i p te m p e r a t u r e a t 6 O ' C (3 3 3 K ) , p r o d u c i n g a constant scale factor set by two external resistors.

Referring to figure 1 , two high gain op amps force the collector currents of the transistor pair to equal the input and reference currents. These currents can be easily generated by externaf resistors since both op amp inputs rest at virtual ground.

I n th e lo g a r i t h m i c m o d e , t h e o v e r a l l c i r c u i t p r o v i d e s t h e tr a n s f e r f u n c t i o n : V . , , , ' k r

I n ( 5 ! r r l ^ ) o r V o , , - K l o g ' o 1 Y l ! - r , . R '

;

Q ' V , ^

H o , , ' " " V r r . r H R r t '

' o'o7 (R' + R')

volts/decade in the case of the 2100.

w n e r e

For most applications, K will be set equal to .lV/decade.

A n o n c h i p 5 V r e f e r e n c e h a s b e e n in c l u d e d f o r a p p l i c a t i o n s n e e d i n g a t r u e lo g , ra t h e r t h a n a l o g r a t i o f u n c t i o n . B o t h l, * a n d 1 " . , s h o u l d b e k e p t a t 1 m A o r le s s f o r b e s t re s u l t s .

2 1 0 0 I n p u t s

T h e 2 1 0 0 , l i k e a l l lo g a m p l i f i e r s , h a s li m i t e d d y n a m r c r a n g e f o r v o l t a g e i n p u t s d u e p a r t i a l l y t o r n p u t o f f s e t v o l t a g e ( w h i c h i s trimmable) and to various second order ef{ects (which are not). Therefore, for widest dynamic range current inputs are r e c o m m e n d e d . S i n c e m o s t w i d e ra n g e t r a n s d u c e r i n p u t s ( s u c h a s p h o t o d i o d e s ) c l o s e l y r e s e m b l e c u r r e n t i n p u t s , t h i s is n o t u s u a l l y a p r o b l e m . U n t r i m m e d , t h e 2 1 0 0 c a n h a n d l e a b o u t 5 d e c a d e s o f d y n a m i c r a n g e i n l o g m o d e , o r a b o u t 1 O d e c a d e s i n lo g ra t i o m o d e . W h e n t r i m m e d , t h i s c a n b e e x t e n d e d t o a t le a s t 6 d e c a d e s ( 1 2 d e c a d e s i n lo g ra t i o m o d e ) .

T h e fo l l o w i n g a p p l i c a t i o n c i r c u i t s a r e , fo r c o n v e n i e n c e , s h o w n f o r v o l t a g e i n p u t s , t h o u g h a l l c o n { i g u r a t i o n s c a n b e u s e d fo r c u r r e n t i n p u t s i n w h i c h c a s e R , ^ c a n b e o m i t t e d . T o e n s u r e u n c o n d i t i o n a l s t a b i l i t y , h o w e v e r , i t is r e c o m m e n d e d t h a t t h e in p u t b e s h u n t e d t o g r o u n d w i t h a 1 O k O r e s i s t o r i n s e r i e s w i t h a 1 0 n F c a p a c i t o r w h e n u s i n g a t r u e c u r r e n t i n p u t .

2 1 0 0 N e g a t i v e S u p p l y

T h e 2 1 0 0 n e g a t i v e s u p p l y i s i n t e r n a l l y r e g u l a t e d a t 7 V , a n d a c u r r e n t l i m i t i n g r e s i s t o r ( R . , " , r ) i s r e q u i r e d i n s e r i e s w i t h p i n 7. For most applications, a v a l u e o f 1 .6 k O f o r 1 5 V s u p p l i e s i s r e c o m m e n d e d . T h e v o l t a g e a t p i n 7 i s t h u s q u i t e s t a b l e a n d is u s e f u l w h e n t r i m m i n g t h e u n i t e x t e r n a l l y .

Power Supply Decoupling and Grounding

B e c a u s e o f t h e h i g h g a i n o f t h e te m p e r a t u r e r e g u l a t o r c i r c u i t , g e n e r o u s p o s i t i v e s u p p l y d e c o u p l i n g s h o u l d b e u s e d ' T h e 0 . 2 p F d e c o u p l i n g c a p a c i t o r s h o w n o n t h e a p p l i c a t i o n c i r c u i t s s h o u l d b e o f c e r a m i c t y p e a n d m o u n t e d a s c l o s e t o p i n s l a n d 4 a s p o s s i b l e . A n a d d i t i o n a l c a p a c i t o r o f a b o u t 5 0 p F o r m o r e s h o u l d a l s o b e in c l u d e d o n t h e b o a r d . l t s h o u l d a l s o b e n o t e d t h a t o i n 1 c a r r i e s a l l th e h e a t e r c u r r e n t , a n d c a r e s h o u l d b e ta k e n w h e n la y i n g o u t g r o u n d l i n e s t o p r e v e n t t h i s fr o m c a u s i n g e r r o r s . T h e n e g a t i v e s u p p l y i s in t e r n a l l y r e g u l a t e d a n d n e e d s n o d e c o u p l i n g .

Temperature Control

The internal chip temperature is regulated at about 60'C but this can be adjusted by means of pin 2. To decrease the t e m p e r a t u r e b y N " C , a r e s i s t o r o f v a l u e " N " M O s h o u l d b e c o n n e c t e d b e t w e e n p i n s 2 and 10. T o in c r e a s e t h e te m p e r a t u r e by N" C, a resistor of value fi Vf l snoutO be connected between pins 2 and 7. The regulator can be shut off entirely with a 1 0 0 k O r e s i s t o r f r o m p i n 2 t o + V . T h i s is u s e f u l i n l o w p o w e r a p p l i c a t i o n s . W i t h n o r e g u l a t i o n , t h e r e f e r e n c e d r i f t is a b o u t 70 ppm/.C, and the scale factor drift about -3300 ppm/'C. The latter can be compensated using a temperature compensating resistor (e.9. Tel Labs Q 81) instead of R'.

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C 5 n F

c - -

2 t ) ( r p F -

T

₌

. A I ] J I - ] S I F O R t ] I I F IR F N ] S C A L E IA C i O B

v , ( ]V'DECADE)

v , , ( 1 0 v M A X )

5 V R E F E R E N C E OI-]IPUI

F I G U R E 2 . I N V E R T I N G L O G A R I T H M I C A M P L I F I E R

1

2 3 4 5 6 7 B

1 6 1 l r 1 4 1 3 1 2 1 t I t l

O 1nF

1 2 3 4 5 6 7 B

1 t i 1 5 1 4 1 3 1 2

il

1 0 9

F .170o

6 ZK', C .

200pF

v , , ( 1 0 v t v A X )

r- g

B . ( r 0 K )

"ADJUST FOR DIFFERENT SCALE FACTOR

C ,

r----t_

5OOpF =

R . , 1 6 K

5 V R E F E R E N C E O U T P U T

I N F II

=

FIGURE 3. NON INVEBTING LOGARITHMIC AMPLIFIER

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Inverting Log Amplifier

F i g u r e 2 s h o w s t h e 2 1 0 0 u s e d in t h e in v e r t i n g l o g m o d e . W i t h l, * - l " r , ( V , " : 1 0 V w i t h v a l u e s s h o w n ) t h e o u t p u t w i l l b e zero, and willincrease at 1V/decade as l,* reduces. The 10V input range optrmizes dynamic range in + 15V systems, but can be changed proportionally by adjusting R,,u. Adjusting R, will alter the scale factor, while adjustment of R"" will alter the output offset at a given V,".

C, C, & C. provide phase compensation for the system, yielding a 30kHz small signal bandwidth at l,N : 'lmA, SkHz at 1,"

: 1pA and '1.6kHz a l l , ^ : 1 0 0 n A . T h i s c a n b e im p r o v e d b y a f a c t o r o f 3 b y in c r e a s i n g C . t o 1 O n F a n d r e d u c i n g C ' t o 2 n F , at the expense of some peaking at the upper range of input current.

N o n I n v e r t i n g L o g A m p l i f i e r

I n t e r c h a n g i n g t h e s i g n a l a n d r e f e r e n c e i n p u t s y i e l d s a n o n in v e r t i n g l o g a m p l i f i e r ( f i g u r e 3 ) . In th i s c a s e th e o u t p u t c r o s s e s zero with the input five decades below full scale, but this can be altered by adjusting R.. A slight inaccuracy is caused by R, and R, adding to the base resistance of the logging transistors, but this is minimized by keeping these as small as o o s s i b l e .

The small signal bandwidth is 5kHz with l,^ from 1 pA to 1mA and is better than 2kHz over the full five decade range.

L o g R a t i o A p p l i c a t i o n s

The 2100 is well suited to log ratio applications where the output is proportional to the logarithm of the ratio of two input currents or voltages. This is because both the signal and reference inputs operate at true virtual ground eliminating the need for a true current found in many other configurations.

However, the output amplifier of the 2100 can only swing about 1.5V below ground and can only sink about 300pA of current. This causes problems if the reference current is more than 1 decade below the signal current.

lf the latter criterion is not exceeded, the circuit of figure 4 is recommended. R. provides the extra sink current to provide a 1 V o u t o u t w i t h an additional 1 0 k lo a d .

lf full{our quadrant capability is necessary, the output buffer shown in figure 5 can be added. This will provide a * 5V output for reference/signal ratios from 105 to 10 5 (a 10 decade dynamic range).

C 2 7rf

I--

- T C

* 20OpF B * 2

V . , , (1 V ' D E C A D E )

V ,. K oq V,iV, (K - I ViDECADE WITH VALUES SHOWN)

FIGURE 4. LOG RATIO AMPLIFIER l

2 3 4 5 6 7 B

1 6 t 5 1 . 1 1 3 1'2 1 1 ] O

I

A D J I I S T F O R L ] I F F E R I . N I S C A L E F A C T O B

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1 6 1 5 1 4 1 3 1 2

I

1 0 I

v ,, ( * 5v NIAX)

.ADJUST FOR DIFFERENT SCALE TACTOR

FIGURE 5. MODIFICATION OF FIGURE 4 FOR FOUR QUADRANT OPERATION

1 6 1 5 1 , 1 1 i l 1 2

il

l(-)

!,

' t 2

1

0

1 1 0 (r

I

c _f-

2 ( i t l r r l

T

V ( ] D t C A D t V O I I )

5 V H L F t t r t f ' J . . l E a J L l T t , l l I

,ADJUST FOR DIFFERENT SCATE tACIOF

F I G U R E 6 . A N T I L O G A R I T H M I C A M P L I F I E R

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470o 1 v 1 6

2 1 5 3 2 1 1

,

' 0

1 1 a 5 0 1 2

( i 1 1

/ 1 0 8 9

1K 470K ^T,

1 0 K 4 7M{L ^T

1 00K 1 0 M o 6 B K

2 0 M o 6B0o . ( C u r r e n t

I n p u t ) R x RY R,n

OUTPI]I OFFST I TR I\/

F I G U R E 7 . T R I M M I N G T H E 2 1 O O

A n t i l o g ( E x p o n e n t i a l ) A m p l i f i e r

F i g u r e 6 s h o w s t h e c o n n e c t i o n s r e q u i r e d t o g e n e r a t e t h e e x p o n e n t i a l f u n c t i o n . T h e in p u t r a n g e a s s h o w n i s z e r o to 1 0 V b u t this can be changed by adjusting R,. The output scale factor is 1 decade/volt but can be changed by adjusting Rorr. The b a n d w i d t h o f th e c i r c u i t i s a b o u t 5 0 O k H z .

Trimming the 2100

Figure 7 shows general trimming techniques for input offset, output offset and scale {actor. The input offset adjustment can b e d u p l i c a t e d f o r th e r e f e r e n c e i n p u t i n th e c a s e o f lo g ra t i o a p p l i c a t i o n s .

The input offset trim removes errors due to both amplifier offset and input bias current, and the use of the positive and negative reference voltages gives a high rejection to supply voltages changes.

U n l i k e a n o p a m p , a l o g a m p c a n n o t b e t r i m m e d w i t h V , * - 0 s i n c e t h e lo g o f z e r o th e o r e t i c a l l y g i v e s an infinite o u t p u t voltage. A suggested technique is to trim output offset and scale factor first, and then apply a small signal to the input and adjust the input offset trim for correct reading at the output.

Micro Technologry SSM

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