8XC52/54/58 HARDWARE DESCRIPTION

INTRODUCTION

The 8XC52/54/58 is a highly integrated 8-bit rnicro-controlkx bed ontheMCSQ-51 architecture. The key featuresare an enhanced serial pOrtfor multi-processor communications and an up/down timer/counter. As this product is CHMOS, it has two software selectable reduced power modes: Idle Mode and Power Down Mode. Being a member of the MCS-51 family, the 8XC52/54/58 is optimized for control applications.

This document presents a comprehensive description of the on-chip hardware features of the 8XC52/54/58 as they ditTerfrom the 80C51BH. It begins by describing how the 1/0 functions are different and then discusses each of the peripherals as follows:

● 256 Bytes on-chip RAM

● Special Function Registers (SFR)

● Timer 2

— Capture Timer/Counter

— Up/Down Timer/Counter

— Baud Rate Generator

ble Serial Interface with

● Full-Duplex Programma

— Framing Error Detection

— Automatic Address Recognition

● 6 Interrupt Sources

. Enhanced Power Down Mode

● Power Off Flag

● ONCE Mode

The 8XC52/54/58 uses the standard 8051 instruction set and is pin-for-pin mmpatible with the existing MCS-51 family of products. Table 1 summarks the product names and memory differences of the various 8XC52/54/58 products currently available. Through-out this documentj the products will generally be re-ferred to as the 8XC5X.

Table1.8XC52/54/58Microcontrollers

~ ROM

I

EPROM I ROMlessl ROM/EPROM I RAM

1

Device Version Version Bytes Bytes

80C52 87C52 80C32 8K 256

80C54 87C54 80C32 16K 256 80C58 87C56 80C32 32K 256 For a description of the features that are the same as the 80C51, the reader should refer to the MCS-51 Ar-chitectural Overview, MCS-51 ProgrammersGuide/

Instruction Set, and the Hardware Description of the 80C51 in the Embedded Microcontrollers ~d pr~

PIN DESCRIPTION

The8XC5Xpin-out is the same as the 80C51. The only dit%rence is the rdternate function of pins P1.O and P1.1. P1.Ois the external clock input for Timer 2. P1.1 is the Reload/Capture/Direction Control for Timer 2.

DATA MEMORY

The8XC5X implements 256 bytes of on-chip RAM.

The upper 128 bytes occupy a parallel address space to the Special Function Registers. That means they have the same addresses, but they are physically separate from SFR space.

When an instruction acceaaesan internal location above address 7FH, the CPU knows whether the access is to the upper 128 bytes of RAM or the SFR space by the addressing mode used in the instruction. Instructions that use direct addressingaccess SFR space. For exam-ple,

MOV OAOH,#data (Direct Addressing)

accesses the SFR at location OAOH(which is P2). In-structions that use indirect addressing access the upper

128 bytes of W. For example,

MOV @RO, #data (Indirect Addressing)

where ROcontains OAOH,accesses the data byte at ad-dress OAOH,rather than P2 (whose adad-dress is OAOH).

Note that stack operations are examples of indirect ad-dressing, so the upper 128 bytea of data RAM are avail-able as stack space.

SPECIAL FUNCTION REGISTERS

A map of the on-chip memory area called the Special Function Register (SFR) space is shown in Table 2.

Notethst not all ofthe addreaaesare

occupied,Unoc-cupied addresses may not be implemented on the chip.

Read accesses to these addresses will in general return random dam and write amesses will have an indetermi-nate effect.

User software should not write 1s to these unlisted lo-cations, since they may be used in future MCS-51 prod-ucts to invoke new features. In that case the reset or inactive values of the new bits will always be O.

intd.

8XC52/54/58 HARDWARE DESCRIPTION

Table2. 8XC5XSFRMapandResetValues OF8H

T2CON T2MOD RCAP2L RCAP2H TL2 TH2 OoooooooXxxxxxoo 00000000 0000000000000000 00000000

1P SADEN

TCON TMOD TLO TL1 THO TH1

00000000 00000000 Ooooooo0 0000000000000000 OoOmooo

Po SP DPL DPH PCON

11111111 00000111 00000000 00000000 00000000 OFFH TimerRegist ers-flmtrol and status bits areeontairred InterruptRegiate-The individual interrupt enable in registersT2CON and T2MOD for Timer 2. The reg- bits are in the IE register. Two priorities can be set for ister pair (RCAP2H, RCAP2L) are the Capture/Re- each of the 6 interrupt sources in the IP register. The load registersfor Timer 2 in Id-bit capture mode or 16- IPH register allows four priorities.

bit aut&reload mode.

Serial Port Regiaters-RegM.ers SADDR and SA- TIMER 2

DEN are used to define the Given and the Broadcast

addresses for the Automatic Address Recognition fea- Timer 2 is a id-bit Timer/Counter which can operate

ture. either as a timer or an event counter. This is selectable

by bit Cm in the SPR T2CON (Table 3). It has three

4-4

i~e

8XC52/54/58 HARDWARE DESCRIPTION operatingmodes:Captur%auto-reload (up or down

counting), and baud rate generator.The modes are ae-lected by bits in T2CON as shown in Table 4.

Timer 2 consists of two 8-bit registers, TH2 and TL2.

In the Timer function, the TL2 register is incremented every machine cycle. Thus one can think of it as count-ing machine cycles Siuce a machine cycle consists of 12 oscillator perioda, the count rate is 1/12of the oscillator frequency.

ternaf input pin, T2. In this function, the external input is sampled during S5P2 of every machine cycle. When the samples show a high in one cycle and a low in the next cycle, the count is irtcremented.The new count value appears in the register during S3P1 of the cycle following the one in which the transition was detected.

Since it takes 2 machine cycles (24 oscillator periods) to

~- a l-to-o transition, the maximum count m~

IS1/2,of the oscillator frequency. To ensure that a given level is sampled at least once before it changes, it should be heid for at least one fidl machine cycl;.

In the Counter function, the register is incremented in response to a l-to-O transition at its corresponding

ex-Table 3. T2CON—Timer/Counter 2 Control Reaieter

T2CONAddress= OC8H ResetValue= 0000OOOOB

BitAddressable

TF2 EXF2 RCLK TCLK EXEN2 TR2 cPfm cP/m

Bit 7 6 5 4 3 2 1 0

Symbol Function

TF2 Timer2 overflowflagsetbya Timer2 overflowandmustbe clearedbysoftware.TF2 willnotbe setwheneitherRCLK= 1 orTCLK= 1.

EXF2 Timer2 externalflag set wheneithera captureor reloadia causedby a negative transitiononT2EXandEXEN2= 1. WhenTimer2 interruptisenabled,EXF2= 1 will causethe CPUto veetorto the Timer2 interruptroutine.EXF2mustbe clearedby software.EXF2doesnotcausean interruptinup/downcountermode (DCEN = 1).

RCLK Receiveclockenable.Whense~causestheserialportto useTimer2 overflowpulses foritsreceiveclockin serial portModes 1 and 3. RCLK = Ocauses Timer1 overflowto be usedforthereceiveclock.

TCLK Transmitclockenable.Whenset,causestheserialportto useTimer2 overflowpulses foritstransmitclockinserial port Modes 1 and 3. TCLK = (1~usgs Timgr 1 ovgrflows to be usedforthetransmitclock.

EXEN2 Timer2 externalenable.Whenset,allowsa ~pture or reloadto occurss a resultof a negativetransitiononT2EXifTimer2 isnotbeingusedto clocktheserialport.EXEN2

= OcausesTimer2 to ignoreeventsat T2EX.

TR2 Start/StopcontrolforTimer2. TR2 = 1 startsthetimer.

cm!

TimerorcounterselectforTimer2.C/~ = Ofortimerfunction.C/~ = 1 forexternal eventcounter(fallingedgetriggered).

cPlm Capture/Reloadselect.CP/~ = 1 causescapturesto occuronnegativetransitions at T2EXif EXEN2= 1. CP/~ = Ocausesautomaticreloadsto occurwhenTimer2 overflowsor negativetransitionsoccurat T2EXwhenEXEN2= 1. WheneitherRCLK or TCLK= 1, thisbit is ignoredandthe timerisforcedto auto-reloadon Timer2 overtlow.

8XC52/54/58 HARDWARE DESCRIPTION

Table 4. Timer 2 Operating Modes

RCLK + TCLK cPlm TR2 MODE

o 0 1

16-BitAuto-Reload

I ^o I

¹ Ill 16-BitCapture I

I

¹ I

x

Ill BaudRateGenerator I

I x I x Iol

oft-l

I

CAPTURE MODE

Inthe capture mode there are two options selected by bit EXEN2 in T2CON. If EXEN2 = O, Timer 2 is a 16-bit timer or counter which upon overfiow sets bit TF2 in T2CON. This bit can then be used to generate an interrupt. If EXEN2 = 1, Timer 2 still does the above, but with the added feature that a 1-to-Otran-sition at external input T2EX eauaes the current value in TH2 and ‘fZ2 to be captured into RCAP2H and RCAP2L, respectively. In additio~ the transition at T2EX esuaes bit EXF2 in T2CON to be set. The EXF2 bit, like TF2, ean generate an interrupt. The capture mode is illustrated in Figure 1.

AUTO-RELOAD (Upor Down Counter) Timer 2 can be programmedto count up or down when contlgursd in its 16-bit auto-reload mode. This feature

is invoked by a bit named DCEN (Down Counter En-able) located in the SFR T2MOD (see Table 5). Upon reset the DCEN bit is set to O so that Timer 2 wilf default to count up. When DCEN is set, Timer 2 can count up or down depending on the value of the T2EX pin.

Figure 2 shows Timer 2 automatically counting up when DCEN = O.In this mode there are two options selected by bit EXEN2 in T2CON. If EXEN2 = O, Timer 2 counts up to OFFFFH and then sets the TF2 bit upon overflow. The overtlow also causes the timer registers to be reloaded with the 16-bit value in RCAP2H and RCAP2L. The values in RCAP2H and RCAP2L are preset by software. If EXEN2 = 1, a 16-bit reload can be triggered either by an overfiow or by a l-to-O transition at external input T2EX. This transition also sets the EXF2 bit. Eoth the TF2 and EXF2 bita ean generate an intemupt if enabled.

OJ

^{c/E =1 TR2I CONTROL}

-.m-..--T2 PIN ^{LAt’l UKt.}I II

TRANSITION

OUECTION

piaiim ^I

^{INTERRUPTTIMER2}

⁺

T2EX PIN

+X1 ~ I

I CONTROL

EXEN2

2707S3-1

Figure1.Timer2 inCaptureMode

4-6

i@. 8XC52/54/58 HARDWARE DESCRIPTION

--- -. .--- ... . - --- ---

..-=---T2MODAddress= OC9H ResetValue= )(XXXXXOOB

NotBitAddressable

— — — — — — T20E DCEN

Bit 7 6 5 4 3 2 1 0

8ymbol Function

Notimplemented,reservedforfutureuse.

T20E Timer2 OutputEnablebit.

DCEN Whenset,thisbitallowsTimer2 to be configuredas an up/downcounter.

d

cm=1

OVERFLOW TR2

RELOAD T2 PIN

TIMER2 INTERRUPT TRANSMON

DEI’ECTION

T2EX PIN I+q

I CONTROL EXEN2

2707S2-2

Figure 2. Timer2 Auto Reload Mode (DCEN = O)

(DOWN COUNTINGRELOADVALUE) TOGGLE

1 OFFH 1 OFFH [

&f

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