CCF4 CCF3 CCF2 CCF1 CCFO
PCACounterOverflowflag.Setbyhardwarewhenthe counterrollsover.CFflagsan interruptif bit ECFin CMODis set.CFmaybeset byeitherhardwareor softwarebutcan onlybe clearedbysoftware.
PCACounterRuncontrol bit. Set by software to turnthe PCAcounteron. Mustbe cleared bysoftwareto turnthe PCAcounteroff.
Notimplemented,reservedfor futureuse”.
PCAModule4 interruptflag.Setbyhardwarewhena matchor captureoccurs.Mustbe clearedbysoftware.
PCAModule3 interruptflag.Setby hardwarewhena matchor captureoccurs.Mustbe clearedbysoftware.
PCAModule2 interruptflag.Setbyhardwarewhena matchor captureoccurs.Mustbe clearedbysoftware.
PCAModule1 interruptflag.Setby hardwarewhena matchor captureoccurs.Mustbe clearedbyeoftware.
PCAModuleOinterruptflag.Setby hardwarewhena matchor captureocours.Mustbe clearedbysoftware.
UsersoftwareshouldnotwriteIs to resend bits,Thesebitsmaybeusedinfuture8051familyproductstoinvoke new features.In that case, the reset or inaotive value of the new bit will be O, and its active value will be 1. Thevalue read from a reserved bit is indeterminate.
Each of the five compare/capture modules has six pos-sible functions it can perform:
— Id-bit Capture, positive-edge triggered
— l~bit Capture, negative-edge triggered
— 16-bit Capture, both positive and negative-edge triggered
— 16-bit Software Timer
— 16-bit High Speed Output
— 8-bit pulse WidthModulator.
In addition, module 4 can be used as a Watchdog
Time-r. Themodules canbeprogrammed in
snycombina-tion of the different modes.
Each module has s mode register called CCAPMn (n = O, 1, 2, 3, or 4) to select which fimction it will perform. The CCAPMn register is shown in Table 12.
Note the ECCFn bit which enables the PCA interrupt
6.2 Capture/Compare Modules when a module’s event flag is set. The event flags (CCFn) are located in the CCON register and get set when a capture event, software timer, or high speed outputevtit occurs for a given module. - -Table 13 shows the combinations of bits in the CCAPMn register that are valid and have a defined function. Invalid combinations will produce undefined results.
Each module also has a pair of 8-bit compsre/capture
registers (CCAPnH and CCAPnL) associated with it.
Theseregisters store the time when a capture event
oc-curred
orwhena compare eventshouldoccur.Forthe
PWMmode, the high byte regiser CCAPnH controls the duty cycle of the wsveform.
The next five sections describe each of the compare/
capture modes in detail.
5-22
8XC51FXHARDWAREDESCRIPTION
Table 12. CCAPMn: PCA Modules Compare/Capture Regiatere
CCAPMn Address CCAPMO ODAH Reset Value = XOOO00006
(n = O-4) CCAPMI ODBH
CCAPM2 ODCH CCAPM3 ODDH CCAPM4 ODEH Not Bit Addressable
— ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn
Bit 7 6 5 4 3 2 1 0
Symbol Funotion
— ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn NOTE:
Notimplemented,reservedfor futureuse*.
Enablecomparator.ECOMn= 1 enablesthe comparatorfun~”on.
CapturePositive,CAPPn= 1 enablespositiveedgecapture.
CaptureNegative,CAPNn= 1 enablesnegativeedgecapture.
Match.WhenMATn= 1,a matchofthe PCAcounterwiththismodule’scompare/cepture registercausesthe CCFnbit inCCONto be set,flaggingan interrupt.
Toggle.WhenTOGn= 1,a matchofthe PCAcounterwiththismodule’scompare/capture registercausesthe CEXnpinto toggle.
Pulse Width Modulation Mode. PWMn = 1 enables the CEXn pinto be usedas a pulsewidth modulatedoutput.
EnableCCFinterrupt.Enablescompare/captureflagCCFnintheCCONregisterto generate an interrupt.
*User softwareshoutdnot write Is to reservedbits.These bite may be used in future8051 familyproductsto invoke new features.In that case, the reset or inscttie valueof the new bit will be O,and its acfNe value willbe 1. The value read from a reservedbit is indeterminate.
Tabfe 13. PCA Module Modes (CCAPMn Regiater)
I
- lECOMnlCAPPnlCAPNnlMATnl TOGnlPWMnlECCFnl ModuleFunctionI
I x I o I o I o I o I O I o I o INoot)erstion I
x x
1 0 0 0 0x
16-bit capture by a postive-edgetriggeron CEXnx x o 1 0 0 0 x Ie-bitcapturebya negative-edgetriggeronCEXn
x x
1 1 0 0 0 x 16-bifcapturebyatrsnsition onCEXnx 1 I o 0 1 I Ololx 16-bifSoftwareTimer
x
1 0 0 1 1 0 x 16-bit High Speed Outputx I[ 1 I1 o 1 0 1 0 1 0 1 1 t 0 !8-bit PWMI
x 1 0 0 1 x Olx WatchdogTimer
X = Don’t Care
i~o
8XC51FXHARDWAREDESCRIPTION6.3
16-Bit Capture ModeBothpositiveandnegativetransitionseantriggera cap-turewith thePCA. This gives the PCA the flexibility to measure perio& pulse widths, duty cycles, and phase differences on up to five separate inputs. Setting the CAPPn snd/or CAPNn in the CCAPMn mode register select the input trigger-positive snd/or negative tran-sition-for module n. Refer to Figure 17.
The external input pins CEXOthrough CEX4 are sam-pled for a transition. When a valid transition is detected (psitive rind/or negativeedge),hardware loads the 16-bit vrdueof the PCA timer (CH, CL) into the mod-de’s capture registers (CCAPnH, CCAPnL). The re-sulting value in the capture registers reflects the PCA timer value at the time a transition was detected on the CEXn pin.
Upon a capture, the module’s event flag (CCFn) in CCON is set, and an interrupt is flagged if the ECCFn bit in the mode regista CCAPMn is set. The PCA in-terrupt will then be generated ifit is enabled. Since the hardware does not clear an event tlag when the inter-rupt is vectored to, the tlag must be cleared in software.
In the interrupt service routine, the lt%it capture value must be saved in IL4M before the next captureevent ocours.A subsequent capture on the same CEXn pin will write over the first capture value in CCAPnH and CCAPnL.
6.4
16-Bit Software Timer ModeInthe eotnpare modej the 16-bitvalue of the PCA tim-er is compared with a 16-bit value pm-loaded in the module’s compare registers(CCAPnH, CCAPnL). The comparison oeours three times per machine cycle in order to recognize the fastest possible clock input (i.e.
~. x oscillator frequency). Setting the ECOMn bit in the mode register CCAPMn enables the comparator function as shown in Figure 18.
For the Software Timer mode, the MATn bit also needs to be set. When a match occurs between the PCA timer and the compare registen, a match signal is generated and the module’s event flag (CCFn) is set. An interrupt is then flagged if the ECCFn bit is set. The PCA inter-rupt is generated ordy if it has been properly enabled.
software must clear the event flag before the next inter-rupt will be flagged.
——
+-l 1/1
1ICEXn&
PIN
+KJ
I /1 II
I
+-’N”RRUM
z
CH :I CL llMER/COUNIERPCA8 8
CAPTURE
GGl
I I I
I x
I
oI
oI
o ECCFn n = O, 1, 2, 3 or4CCAPMnMOOEREGISTER x = OOtrt Care
270653-14 Figure 17.PCA16-Bit Capture Mode
5-24
intel.
8XC51FXHARDWAREDESCRIPTIONDuring the interrupt routine, a new 16-bit compare vaf- regularhold-off signals to the Watchdog. Thesecirctits
ue canbe written to the compareregisters (CCAPnH are used in applications that are subject to electrical and CCAPnL). Notice, however, that a wn”te to noisq power glitches, electrostatic diseharg% etc., or CCAPnL clears the ECOMn bit which temparily dir- where high reliability is required.
ables the companstorjimction while these registens are
being updated so an invalid match does not occur. A The Watchdog Timer function is only available on write to CCAPnH sets the ECOMn bit and re-enables PCA module 4. In this mode, every time the count in the comparator. For this reason, user software should the PCA timer matchea the value stored in module 4’s write to CCAPnL first, then CCAPnH. compare registers, an internal reset is generated. (See Figure 19.) The bit that selects this mode is WDTE in the CMOD register. Module 4 must be setup in either
6.5
High Speed Output Mode comparemode as a SoftwareTimer or High Speed Out-put.The High Speed Output (HSO) mcde toggles a CEXn
pin when a match occurs between the PCA timer and a When the PCA Watchdog Timer timea out, it resets the pm-loaded value in a module’s compare registers. For chip just like a hardware re@ except that it doea not this mode, the TOGn bit needs to be set in addition to drive the reset pin high.
the ECOMn and MATn bits as seen in Figure 18. By
setting or clearing the pin in software, the user can To hold off the reset, the user has three options:
select whether the CEXn pin will change from a logical
O to a logicaf 1 or vice versa. The user rdso b the (1) periodically change the compare value so it will option of flagging an interrupt when a match event oc- never match the PCA timer,
curs by setting the ECCFn bit. (2) periodically change the PCA timer vafue so it will never match the compare value,
The HSO mode is more accurate than toggling port (3) disable the Watchdog by clearing the WDTE bit pins in software because the toggle occurs before before a match occurs and therrfater re-enable it.
branching to an interrupt. That iy interrupt latency
will not effect the accuracy of the output. If the user The first two options are more refiable because the does not change the compare registers in an interrupt Watchdog Timer is never disabled as in option #3. The routin~ the next toggle will occur when the PCA timer second option is not recommended if other PCA mod-rolls over and matches the last compare value. ules are being used since this timer is the time base for all five modules. Thus in most applications the first solution is the best option.
6.6 Watchdoa Timer Mode
IfaWatchdog Timer is not needed, modufe 4 can still A Watchdog Timer is a circuit that automatically in- be used in other modes.
vokea a reset unless the system being watched sends
PT
PCA
l’ws/cou PIN
270S5S-15
Figure 18. PCA 18-Bit Comparator Mode: Software Timer and High Bpeed Output
8XC51FXHARDWAREDESCRIPTION
6.7
Pulse Width Modulator ModeAny or all of the five PCA modules can be pro-p~ to be
a PukeWidthModulator.
The PWM output can be used to convert digital data to an analog signal by simple externalcircuitry. The frequencyof the PWM depends on the clock sources for the PCA timer.With a 16 MHz crystal the maximum frequency of the PWM waveform is 15.6 KHz.
The PCA generates8-bit PWMS by comparing the low byte of the PCA timer (CL) with the low byte of the module’s compareregisters(CCAPnL). Refer to Figure 20. When CL < CCAPnL the output is low. When CL
> CCAPnL the output is high. The value in CCAPnL controls the duty cycle of the waveform. To change the value in CCAPnL without output glitches, the user must write to the high byte register (CCAPrsH). This value is then shifted by hardware into CCAPnL when CL rolls over from 01%-I to WIHwhich corresponds to the next period of the output.
wDSS
PCA
I
xI* I
KO1441 o I o I 1 I x I o I xI
CC4PM4 MODEREOISTER RSsEl
WRm TO
CCAP4L ,, ,,0
WRmm
CCAP4H