w’
ema OmE(n om.Y m
n=
Olmcl &
INOIRECT AwnEaslNG 00.
FFFl
64K m-me ExnmNAL
270249-4 Figure 3b. The 8052 Date Memory
i~. MCS@-51PROGRAMMER’S GUIDE AND INSTRUCTION SET
INDIRECT ADDRESS AREA:
Note that in Figure 3b the SFRSand the indirect address RAM have the same addreasea(80H-OFFH).Neverthe-less, they are two separate areas and are amesaed in two diiferentways.
For examplethe instruction MOV 8oH,#o&lH
writesOAAHto Port Owhichis one of the SFRSand the instruction MOV Rr),#80H
MOV @RO,#OBBH
writesOBBHin location 80H of the data RAM. Thus, after executionof both of the aboveinstructionsPort Owill contain OAAHand location 80 of the MM will contain OBBH.
Note that the stack operationsare examplesof indirect addressing,so the upper 128bytesof data MM are available as stack space in those deviceswhich implement 256 bytesof internal RAM.
DIRECT AND INDIRECT ADDRESS AREA:
The 128bytesof W whichcan be ameasedby both direct and indirect addressingcan be dividedinto 3 segments as listedbelow and shownin Figure 4.
1. Registar BanksO-3:LocationsOthrough lFH (32bytes).ASM-51and the deviceafter reset defaultto register bank O. To use the other register banks the user must select them in the software (refer to the MCS-51Micro AssemblerUser’s Guide). Each register bank contains 8 one-byteregisters, Othrough 7.
Resetinitiahzesthe StackPointerto location 07H and it is incrementedonceto start from location08H whichis the first register(RO) of the secondregister bank. Thus, in order to use more than one register bank, the SP shouldbe intiaked to a different locationof the RAM where it is not used for data storage (ie, higher part of the WNW).
2. Bit AddressableArex 16 bytes have been assignedfor this segment,20H-2FH.Each one of the 128bits of this wgmmt can be directly addressed(0-7FH).
The bits can be referredtoin two ways both of which are acaptable by the ASM-51.One way is to refer to their address ie. Oto 7FH. The other way is with referenceto bytes20H to 2FH. Thus,bits O-7 can alsobe referred to as bits 20.0-20.7, and bits 8-FH are the same as 21.0-21.7 and so on.
Each of the 16bytes in this segmentcan also be addressedas a byte.
3. Scratch Pad Arex Bytes30H through 7FH are availableto the user as &ta MM. However,if the stack pointex has been initializedto this arm enough number of bytes shouldbe left aside to prevent 5P data destruction.
2-6
in~.
MCS@-51PROGRAMMER’SGUIDE AND INSTRUCTION SET Figure4 shows the difYerentsegmentsof the on-chipRAM.sol
4SI
14P
1.7
I3F
SCRATCH Pm ARSA
301
2s . . . 7F 2P
AaaRLLs
20
0... 27 SSGMENT
18 3 IF
10 2 1? RSGISIER
0s 1 OF BANKS
00 0 07
270249-5 Figure 4.128 Bytes of RAM Direct and Indirect Addreeesble
in~.
MCS@-51PROGRAMMER’S GUIDE ANDINSTRIJCTlON SETSPECIAL FUNCTION REGISTERS:
Table 1 containsa list of all the SFRs end their addressee.
ComparingTable 1and Figure 5 showsthat all of the SFRs that are byteand bit addressableare locatedon the first col~n of-the diagram in Figure 5.
Symbol Data Pointer2 Bytes LowByte Timer/Counter Mode Control Timer/Counter Control Timer/Counter 2 Control Timer/Counter O HighByte Timer/Counter O LowByte Timer/Counter 1 HighByte Timer/Counter 1 LowByte Timer/Counter 2 HighByte Timer/Counter 2 LowByte T/C 2 Capture Reg. HighByte T/C 2 Capture Reg. LowByte SerialControl
Serial Data Buffer
PCON PowerControl
int&
M~@.51 PROGRAMMERS GUIDE AND INSTRUCTION SETWHAT DO THE SFRS CONTAIN JUST A~ER POWER-ON OR A RESET?
Table 2 lists the contents of each SFR after power-onor a hardware reset.
Table 2. Conte Register
“ACC
“B
*PSW SP DPTR
DPH DPL
*PO
*P1
*P2
*P3
*IP
*IE TMOD
●TCON
●+T2CON THO TLO TH1 TL1 +TH2 +TL2 +RCAP2H +RCAP2L
●SCON SBUF PCON
= Undefined
= BitAddreassble + = 8052only
) of the SFRS after reset Value in Binary 00000000 00000000 00000000 00000111 00000000 00000000 11111111 11111111 11111111 11111111 8051 XXXOOOOO, 8052 XXOOOOOO 8051 OXXOOOOO, 8052 OXOOOOOO 00000000
00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Indeterminate HMOS OXXXXXXX CHMOS OXXXOOOO
intd.
M(3%51 PROGRAMMERS GUIDE AND INSTRUCTION SETSFR
F8 FO E8 EO D8 DO C8 co B8 BO A8 AO 98 90 88 80
MEMORY MAP
8 Bytes
B ACC Psw
T2CON RCAP2L RCAP2H TL2 TH2
1P P3 IE P2
SCON SBUF
PI
TCON TMOD TLO TL1 THO TH1
Po SP DPL DPH PCON
FF F7 EF E7 DF D7 CF C7 BF B7 AF A7 9F 97 8F 87
-r
Figure 5Bit
Addressable
2-1o
i~.
M=@-51 PROGRAMMER’S GUIDE AND INSTRUCTION SETThose SFRsthat havetheir bits assignedfor variousfunctionsare listedin this section.A briefdescriptionof each bit is providedfor quick reference.For more detailed informationrefer to the Architecture Chapter of this book.
PSW: PROGRAM STATUS WORD. BIT ADDRESSABLE.
CY AC FO RS1 RSO Ov I — I P
CY PSW.7 CarryFlag.
AC PSW.6 AuxiliaryCarry Flag,
FO PSW.5 Flag Oavailableto the user for generalpurpose.
Rsl PSW.4 RegisterBank selector bit 1 (SEE NOTE 1).
Rso PSW.3 RegisterBank selector bit O(SEE NOTE 1).
Ov PSW.2 OverflowFlag.
— Psw.1 User definableflag.
P Psw.o Parity flag. Set/cleared by herdwareeach instructioncycleto indicateerrodd/werr number of
‘1’bita in the accumulator.
NOTE:
1. ThevaluepresentedbyRSOandRS1selectsthecorrespondingregisterbank.
RS1 RSO Register Bank Address
o 0 0 OOH-07H
o 1 1 08H-OFH
1 0 2 10H-17H
1 1 3 18H-l FH
PCON: POWER CONTROL REGISTER. NOT BIT ADDRESSABLE.
SMOD I — I — I — GF1 GFO PD IDL
SMOD Double baud rate bit. If Timer 1 is used to generatebaud rate end SMOD = 1, the baud rate is doubled when the SeriatPort is used in modes 1, 2, or 3.
— Not implemented,reservedfor future w.*
— Not implemented,reservedfor future w.*
— Not implemented,reservedfor future use.”
GF1 General purposeflag bit.
GFO General purposeflag bit.
PD Power Down bit. Setting this bit activates Power Down operation in the 80C51BH.(Availableonly in CHMOS).
IDL Idle Modebit. %.ttittgthis bit activatesIdle Modeoperationin the 80C51BH.(Availableonlyin CHMOS).
If 1sare writtento PD andIDL at the sametimejPD tske$precedence,
●Usersoftwareshouldnotwrite1s to reservedbita.Thaeebitsmaybe usedin futureMCS-51productsto invokenew featurea.In thatcase,theresetor inactivevalueofthe newbitwillbeO,anditsectivevaluewillbe 1.
irltele
McS@-51PROGRAMMER’SGUIDE AND INSTRUCTION SETINTERRUPTS:
In order to use any of the interrupts in the MCS-51,the followingthree steps must be taken.
1. 3et the EA (enableall) bit in the IE register to 1.
2. Set the correspondingindividualinterrupt enablebit in the IE register to 1.
3. Begintheinterruptserviceroutineat the em-respondingVector Addressof that interrupt. SeeTablebelow.