Priority Level Structure

Each interrupt source can also be individually pro-_ed to one of two priority levels, bysettingor

clearing a bit in the Intemupt Priority (1P) register shown in Table 18. A low-priority interrupt can itself be interrupted by a higher priority interrupt, but not by another low-priority interrupt. A high priority inter-rupt CSIUIOt be interrupted by my Other interrupt source.

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8XC51FXHARDWAREDESCRIPTION

Table 17. IE: Interrupt Enable Register

IE Address= OA8H ResetValue= 000000006

Bit Addressable

I EA EC ET2 ES ETl EX1 ETo Exo

Bit 7 6 5 4 3 2 1 0

EnableBit = 1 enablesthe interrupt.

EnableBit = Odisablesit.

Svmbol Function EA

EC ET2 ES ETl Exl HO EXO

Globaldisablebit. If EA = O,all Interruptsaredisabled.If EA = 1,eachInterruptcan be individuallyenabledor disabledbysettingor clearingitsenablebit.

PCAinterruptenablebit.

Timer2interrupt enable bit.

SerialPorfinterruptenablebit.

Timer1 interruptenablebit.

Externalinterrupt1 enablebit.

TimerOinterruptenablebit.

ExternalinterruptOenablebit.

Table 18. 1P:Interrupt PrioritY Re9isters

1P Address = OB8H Reset Value = XOOOOOOOB

Bit Addressable

— PPC PT2 Ps PTl Pxl PTO Pxo

Bit 7 6 5 4 3 2 1 0

PriorityBit = 1assigns highpriority PriorityBit = Oassignslowpriority Symbol Function

— Notimplemented,reservedfor futureuse.*

PPC PCAinterruptprioritybit.

PT2 Timer2 interruptprioritybit.

Ps SerialPortinterruptprioritybit.

PT1 Timer 1 interrupt priority bit.

Pxl Externalinterrupt1 prioritybit PTO TimerOinterruptprioritybit.

Pxo ExternalinterruptOprioritybit.

NOTE:

●User softwareshouldnot wrtte Is to reservedbits.These bits maybe usad in future8051 familyproductsto invoke new features.In that case, the reset or inactivevalue of the new bitwillba O,and its active value willbe 1. The value readfrom a reservedbit is indeterminate.

5-34

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8XC51FXHARDWAREDESCRIPTION

If two requests of different priority levels are received simultaneously, the request of higher priority level is servieed. If requests of the same priority level are re-ceived simultaneously, an internal polling sequence de-termines which request is servieed. Thus within each priority level there is a second priority structure deter-mined by the potling sequence shown in Table 19.

Note that the “priority within level” structure is only used to resolvesimultaneous requestsof thesameprian”-ty level.

Table 19. Interrupt Priority within Level Polling Seauence

1 (Highest) INTO

2 TimerO

3 m

4 Timer1

5 PCA

6 SerialPort

7 (Lowest) Timer2

8XC51FXInterrupt Priority Struoture

In the 8XC51FX, a second Interrupt Priority register (IPH) has been added, increasingthe number of priori-ty levels to four. Table 20 shows this second register.

The added register becomes the MSB of the priority select bits and the existing 1P register acts as the LSB.

This scheme maintains eotnpatibility with the rest of the MCS-51 family. Table 21 shows the bit values and priority levels associated with each combination.

Table 21. Priority Level Bit Values Priority

Bits Interrupt Priority Level IPH.x IP.X

o 0 LevelO (Lowest)

1o11

^{I Levell} I

11 I O I Level2 I

1111 I

Leve13 [Hiahest) I

How Interrupts are Handled

Theinterruptflags

^are sampled at S5P2 of every ma-chine cycle. The samples are polled during the follow-ing machine cycle. The Timer 2 interrupt cycle is slightly different, as described in the Response Time section. If one of the tlags was in a set condition at S5P2 of the precading cycle, the polling cycle will fmd it and the interrupt system will generate an LCALL to the appropriate serviee routine, provided this hard-ware-generated LCALL is not blocked by any of the following conditions:

1. An interrupt of equal or higher priority level is al-ready inprogress.

2. The current (polling) cycle is not the final cycle in the execution of the instruction in progress.

3. The instruction in nroaress is RETI or anv write to the IE or 1P

regiat~rs.-Table 20. IPH: Interrupt Priority High Register

IPH Address = OB7H Reeet Value = XOOO0000

Not Bit Addressable

— PPCH PT2H PSH PTIH PXIH PTOH PXOH

Bit 7 6 5 4 3 2 1 0

Notimplemented,reservedfor futureuse.

PCAinterrupt priority high bit.

Timer2 interruptpriorityhighbit.

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8XC51FXHARDWAREDESCRIPTION

Any of these three conditions will block the generation of the LCALL to the interrupt service routine. Condi-tion 2 ensures that the instrucCondi-tion in progress will be mmpleted before vectoring to any seMce routine. Con-dition 3 ensures that if the instruction in progress is RETI or any write to IE or 1P, then at least one more instruction will be executed before any interrupt is vec-tored to.

The polling cycle is repeated with each machine CYC1%

and the values polled are the values that were present at S5P2 of the previous machine cycle. If the interrupt fig for a Zeve/-sensitiveexternal interrupt is active but not being responded to for one of the above conditions and is not still active when the blocking wndition is removed, the denied interrupt will not be serviced. In other worda, the fact that the interrupt flag was once active but not serviced is not remembered. Every poll-ing cycle is new.

The polling cycle/LCALL sequence is illustrated in Figure 25.

Note that if an interrupt of a higher priority level goes active prior to S5P2 of the machine cycle labeled C3 in Figure 25, then in awordance with the above rules it will be vectored to during C5 and C6, without any in-struction of the lower priority routine having been exe-cuted.

Thus the proceasor acknowledges an interrupt request by executing a hardware-generatedLCALL to the ap propriate servicing routine. The hardware-generated LCALL pushes the contents of the Program Counter onto the stsck (but it does not save the P3W) and re-loads the PC with an address that depends on the source of the interrupt being vectored to, as shown in Table 22.

. Interrupt ~ Interrupt

Dans le document MCS@51 MICROCONTROLLER FAMILY USER’S MANUAL (Page 195-198)