USER INTERFACE INTERRUPT CONTROL REGISTER

31 2827 201⁰

-

^{16151413 2 1 0}

bb+4

0 l _. I I ^{j I /01} 1 ^{0 oj}

INTR ABORT <7:4>

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INTR COMPLETE <"4>

INTR SENT <7:4>

INTR FORCE <7:4>

EXTERNAL VE::TO~

VEC70R

The User Interface Interrupt Control Register controls the operation of interrupts initiated by the user interface. In the following discussion, the phrase "interrupt request" refers to interrupts initiated either by the assertion of any of the BCI INT<7:4> L lines or by the setting of any of the force bits in this register.

Bits: 31:28 Name: INTR Abort <7:4> (INTRAB) Type: WIC, DCLOC, SC

l

The four INTR Abort bits correspond to the four interrupt levels. An INTR Abort bit is set if an INTR command sent under the control of this register is aborted (that is, a NO ACK or illegal confirma-tion ..

code is received). INTRAB is a status bit set by the BIIC and can be reset only by the user interface. The bit has no effect on the ability of the BIIC to send or respond to further INTR or IDENT transactions.

Bits: 27:24' Name: INTR Complete <7:4> (INTRC) Type: WIC, DCLOC, SC

The four INTR Complete bits correspond to the four interrupt levels.

An INTR Complete bit is set when the vector for an interrupt has been successfully transmitted or if an INTR command sent under the control of this register is aborted. Removal of the interrupt request clears the corresponding INTRC bit. While an INTRC bit is set, no further interrupts at that level are generated by this register. Further, no IDENTS will be responded to by this register when the INTRC bit is set at the IDENT level.

Bits: 23:20 Name: INTR Sent <7:4> (SENT) Type: WIC, DCLOC, STOPC, SC

The four INTR Sent bits correspond to the four interrupt levels. A set INTR Sent bit indicates that an INTR command for the corresponding level has been successfully transmitted. This bit is cleared during an IDENT command following the detection of a lev€l and master 10

match. Clearing the bit allows the interrupt to be resent if this ..

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7-28

DIGITAL CONFIDENTIAL & PROPRIETARY Digital Internal Use Only

VAXBI REGISTERS

c

_{- node loses the} IDENT arbitration or if the node wins but the vector

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n

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transmission fails. Deassertion of an interrupt request clears the INTR Sent bit.

It is not necessary for the INTR Sent bit at a given level to be set for the BIIC to respond to an IDENT at that level (that is, the interrupt need not have actually been transmitted on the VAXBI). All that is required is that an interrupt request have been posted that matches the IDENT level.

Bits: 19:16 Name: INTR Force <7:4> (FORCE) Type: R/W, DCLOC, STOPC

When set, the BIIC generates interrupts at the specified level. The four INTR Force bits correspond to the four interrupt levels. Setting an INTR Force bit is equivalent to asserting the corresponding BCI INT<7:4> L line.

When multiple interrupt requests are asserted simultaneously, the BIIC transmits INTR commands for the highest priority requests first.

Similarly, when an IDENT command solicits more than one level, the BIIC responds with the highest pending level. (See Section 18.4 for a discussion of the priority of transactions.)

Bit: 15 Name: External vector (EX VECTOR) Type: R/W, DCLOC

When set, the BIIC solicits the interrupt vector from the BCI D<31:0>

H lines (rather than transmitting the vector contained in this control register) in response to an IDENT transaction that matches this register. The BIIC's slave. port asserts an External Vector Selected at Level n EV code the cycle before the vector can be driven on the BCI D lines. A slave port interface using the BIIC must stall the vector at least one cycle (by asserting the STALL code on the RS lines during the IDENT arbitration cycle) before transmitting an ACK (with vector) or a RETRY response.*

Bit: 14 Name: RESERVED and zero Type: RO

*TO comply with VAXBI protocol, BIIC protocol requires a minimum of one STALL cycle before either of these two responses is generated. If no STALL is generated, the BIIC will not properly suppress the transmission of ACK or RETRY CNF codes from nodes that lose the IDENT arbitration during the cycle after the IDENT arbitration. The subsequent collision of CNF codes will then cause bus errors to occur.

7-29

DIGITAL CONFIDENTIAL & PROPRIETARY

Bits: 13:2

Digital Internal Use Only VAXBI REGISTERS

Name: Vector Type: R/W, DCLOC

Contains the vector used during user interface interrupt sequences (unless the External Vector bit is set). The vector is transmitted when this node wins an IDENT arbitration that matches the conditions given in the User Interface Interrupt Control Register.

Bits: 1:0 Name: RESERVED and zeros Type: RO

7-30

DIGITAL CONFIDENTIAL & PROPRIETARY Digital Internal Use Only

VAXBI REGISTERS

C

^7.15 GENERAL PURPOSE REGISTERS

o

o

GENERAL PURPOSE REGISTER 0

bo.-F4 GENERAL PURPOSE REGISTER 1

bo.-F8 GENERAL PURPOSE REGISTER 2

bo.-FC GENERAL PURPOSE REGISTER 3

The use of the general purpose registers is implementation specific.

The type of the bits in these registers isR/W, DeLOe.

Whenever one of these registers is written, a bit is set in the Write Status Register to indicate which register was written.

7-31

DIGITAL CONFIDENTIAL & PROPRIETARY

VAXBI REGISTERS 7.16 SLAVE-ONLY STATUS REGISTER

3' ^{2928 1S17 1312' 1 0}

bb· 100

I . _{I I I}

I ^I I

MEMO~Y SIZE BROKE

MLO·04 . . . . "

The Slave-Only Status Register (SOSR), which is outside BIIC CSR space, is used by slave-only nodes to implement a Broke bit. This register must be implemented by nodes that have a Device Type code with zeros in bits <14:8». When implemented, both the Broke bit and the Memory Size field must have valid values. This register must never be written.

Bits: 31:29 Bits: 28:18

Implementation dependent Name: Memory Size (MSIZE) Type: RO

Indicates the size of the memory as a multiple of 2**18 bytes (256 Kbytes) expressed as a binary number. Slave-only non memory nodes must load the MSIZE field with 0 before or at each transition of the _ Broke bit from set to cleared. When DTYPE<14:8> ⁼ 0 and! ' SOSR<28:18>

=

0, the operating system must treat the node as a\,,,.j' slave-only non-memory device and not as a memory.

Bits: 17:13 Bi t: 12

Implementation dependent Name: Broke

Type: RO, SC When set,

The user self-test.

that BCI DC

indicates that the node has not yet passed its interface must clear this bit when the node has

This bit must be set by the user interface by LO L from the BIIC is deasserted.

Bits: 11:0 Implementation dependent

7-32

sel f-test.

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passed its the time

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DIGITAL CONFIDENTIAL & PROPRIETARY Digital Internal Use Only

VAXBI REGISTERS

Dans le document System Reference Manual (Page 163-168)