FORCE-BIT IPINTR/STOP DESTINATION REGISTER

31

bb+18 O's

Bits: 31:16 Bits: 15:0

1615 0

I

FORCE·ali IPINiRfS70P DES71NAiiON

Name: RESERVED and zeros Type: RO

Name: Force-Bit IPINTR/STOP Destination Type: RjW, DCLOC

Indicates which nodes are to be targeted by force-bit IPINTR or STOP commands sent by this node. Master port IPINTR transactions use command/address data for this field supplied by the user interface.

7-18

DIGITAL CONFIDENTIAL & PROPRIETARY Digital Internal Use Only

VAXBI REGISTERS

C

^7.8 IPINTR SOURCE REGISTER

o

c

c

b~lCI~

_______

IP_tN_T_R_SO_U_R_C_E ______ ~ __________ O_'S _ _ _ _ _ _ ~~! o

~1"5

Bits: 31:16 Name: IPINTR Source Type: WIC, DCLOC, SC

Used by the BIIC to store the decoded ID of a node that sends an IPINTR command to the node. Each bit corresponds to one node on the VAXBI bus. The bit corresponding to the IPINTR master's ID is set when an IPINTR command whose destination matches the ID of this node and whose ID matches a bit in the IPINTR Mask Register is received.

The bit in the IPINTR Source Register is set only if the IPINTR command is received with good parity. It is not required that the IPINTREN bit be set in the BCI Control and Status Register for the appropriate IPINTR Source Register bit to be set.

Bits: 15:0 Name: RESERVED and zeros Type: RO

7-19

DIGITAL CONFIDENTIAL & PROPRIETARY

VAXBI\REGISTERS 7.9 STARTING ADDRESS REGISTER

J13029 1817 0

b~201~0

^__

OI~ __ ~_IA_h_T_IN_G_A_O_D_R_ES_S

^__

~

____________

~_S

_ _ _ _ _ _ _ _ _ _

~I

...0-00:. ...

The Starting and Ending Address Registers define storage blocks in either memory or I/O space.

The Starting and Ending Address Registers must not be configured to include nodespace or multicast space. Software should set up the Starting Address Register before the Ending Address Register to avoid selection problems that may be caused by loading the Ending Address Register with a nonzero value while the Starting Address Register remains cleared.

If the Starting Address Register is set to a value greater than or equal to the contents of the Ending Address Register, no addresses will be recognized.

Bits: 31:30 Bits: 29:18

Name: RESERVED and zeros Type: RO

Name: Starting Address Type: R/W, DeLOe

Determines the address of the first location of a 256-Kbyte block of addresses to be recognized by the BIle for selection of the slave port.

Bits: 17:0 Name: RESERVED and zeros Type: RO

7-20

C·:

^{, ,}

c

o

0",'

^-I

DIGITAL CONFIDENTIAL & PROPRIETARY Digital Internal Use Only

VAXBI REGISTERS 7.10 ENDING ADDRESS REGISTER

.~

31 3029 fB 17 0

b~24~lo __ ^ol~ __

E_N_D'_N_G_A_DD_R_E_ss ___

'~f _____________ ^o'_s~

^________

^~1

The Starting and Ending Address Registers define storage blocks in either memory or I/O space.

The Starting and Ending Address Registers must not be configured to include nodespace or' mul ticast space. Software should set up the Starting Address Register before the Ending Address Register to avoid selection problems that may be caused by loading the Ending Address Register with a nonzero value while the Starting Address Register remains cleared.

If the Starting Address Register is set to a value greater than or equal to the contents of the Ending Address Register, no addresses will be recognized.

Bits: 31:30 Bits: 29:18

Name: RESERVED and zeros Type: RO

Name: Ending Address Type: R/W, DCLOC

Indicates the address that is one greater than the highest address recognized by the BIIC for selection of the slave port. The address must be the first location of a 256-Kbyte block of addresses. For example, if the Starting Address Register contains 1C44 0000 and the Ending Address Register contains 1D68 0000, then the BIIC will recognize addresses 1C44 0000 through 1D67 FFFF for selection of the slave port. The register definition prevents VAXBI accesses to the top 256 Kbytes of I/O space. (This block is also in RESERVED space.) Bits: 17:0 Name: RESERVED and zeros

Type: RO

7-21

DIGITAL CONFIDENTIAL & PROPRIETARY

VAXBI REGISTERS 7.11 BCI CONTROL AND STATUS REGISTER

31 181716 1514:312 11109 8. 7 6 5 ⁴ :3 2 \ ₀

l

^O's

^{I I}

^f

^{I I I Ii I I I I P'l I}

BURST ENABLE

II

IPINTR/STOP FORCE

/

MUL TICAST SPACE ENABLE Bces" ENABLE

STOP ENABLE

I

RESERVED ENABLE IDEN':" EN;.BLE INVAL ENABLE

WRITE INVAL1CATEENABLE

I

USEF; !N1E~F~CE CSj:: SPACE ENABLE

i

BilC ::SR SPACE ENABLE I ^, I

INTFI eNABLE ! ^I

IPiNT" E"';'SLE

I I

_I

PIPELINE NXT ENABL.E I

RiO EV E"lABLE

This re9istei description makes reference to the BCI SEL Land BCI SC<2:0> L lines, which are described in Sections 15.5.4 and 15.5.5.

The followi n 9 cate90ries describe the effects of the enable bits in the BCI control and Status Re9ister on BIIC operation. The cate90ry~ ^J

for each bit is 9iven after the other bit characteristics.

,~

o Disables selection. When a bit of this type is reset, the BIIC both suppresses the appropriate SEL/SC assertion and does not respond in any way to transactions correspondin9 to that enable bit. For example, if the INTREN bit is reset, the node will not be selected for any INTR transactions received from

the VAXBI bus. Most of the enable bits are in this class.

( \

I '

o Special case. Some bits do not simply disable participation.~) Details on how the bit operate~ are in the bit description.

o Not applicable. These bits have no effect on slave selection.

Bits: 31:18 Bi t: 17

Name: RESERVED and zeros Type: RO

Name: Burst Enable (BURSTEN)

Type: R/W, DCLOC - Not applicable

When set, the BIIC asserts BI NO ARB L after the next successf~l arbitration by this node until the BURSTEN bit is reset or BCI MAB L is asserted. The assertion of BCI MAB L does not reset the BURSTEN bit. It merely clears the burst mode state in the BIIC, which is h6ldin9BI NO ARB L. Unless a subsequent transaction clears this bit,f-~' _,~

' , . , / J

7-22

c

C

^"'w

. . ... ,.~

c

DIGITAL CONFIDENTIAL & PROPRIETARY Digital Internal Use Only IPINTR/STOP Command Register), using the Force-Bit IPINTR/STOP Destination Register for the destination field. The IPINTR/STOP Force bit is reset by the BIIC following the transmission of the IPINTR

DIGITAL CONFIDENTIAL & PROPRIETARY

Digital Internal Use Only VAXBI REGISTERS

output of SEL and the IDENT SC code. Therefore, the BIIC will always participate in IDENT transactions that select this node even if this enable bit is reset.

Bi t: 10 Name: INVAL Enable (INVALEN)

Type: R/W, DCLOC - Disables selection

When set, the BIIC asserts SEL and the appropriate SC<2:0> code following the receipt of an INVAL command.

Bit: 9 Name: WRITE Invalidate Enable (WINVALEN) Type: R/W, DCLOC - Special case

When set, the BIIC asserts SEL and the appropriate SC<2:0> code following the receipt of a write-type command whose address does not fall within the bounds set by the Starting and Ending Address Registers, but which has D<29> equal to zero (that is, not I/O space).

Nodes that monitor VAXBI write-type transactions by using the WINVALEN SC code cannot participate in these transactions.

Bi t: 8 Name: User Interface CSR Space Enable (UCSREN) Type: R/W, DCLOC - Disables selection

When set, the BIIC asserts SEL and the appropriate SC<2:0> code following the receipt of a read- or write-type command directed a this node's user interface CSR space.

Bi t: 7 Name: BIIC CSR Space Enable (BICSREN) Type: R/W, DCLOC - Special case

When set, the BIIC asserts SEL and the appropriate SC<2:0> code following the receipt of a read- or write-type command directed at this node's BIIC CSR space. The BIIC's response to BIIC CSR space accesses cannot be disabled; the BIIC always participates in transactions that access its BIIC CSR space.

Note that this bit makes it easy internal registers, as writes same as writes to user interface the slave cannot stall).

to keep "shadow copies" of BIIC to these registers can be treated the CSR space (with the exception that Bi t : 6 Name: INTR Enable (INTREN)

Type: R/W, DCLOC - Disables selection

When set, the BIIC asserts SEL and the appropriate SC<2:0> code following the receipt of an INTR command directed at this node.

Bi ^t: 5 Name: IPINTR Enable (IPINTREN) Type: R/W, DCLOC - Special case

7-24

t

···~'·~.··,·~ , ,

~,

',-DIGITAL CONFIDENTIAL & PROPRIETARY Digital Internal Use Only

VAXBI REGISTERS

When set, the BIIC asserts SEL and the appropriate SC<2:0> code following the receipt of an IPINTR command from a node that is included in the IPINTR Mask Register. The state of this enable bit does not affect whether the node receives IPINTR commands. To ensure that a node does not receive IPINTRs, the user interface should clear the IPINTR Mask Register.

Bi t: 4 Name: Pipeline NXT Enable (PNXTEN) Type: R/W, DCLOC - Not applicable

When set, the BIIC provides an extra BCI NXT L cycle (that is, one more than the number of longwords transferred) during write-type and BDCST transactions. This extra BCI NXT L cycle occurs after the last NXT L cycle for write data and makes i t easier to implement FIFO pointers for some types of master port interface designs.

Bi t: 3 Name: RTO EV Enable (RTOEVEN) Type: R/W, DCLOC - Not applicable

When set, the BIIC outputs the RETRY Timeout (RTO) EV code in place of the RETRY CNF Received for Master Port Command (RCR) EV code following the occurrence of a retry timeout. If the bit is not set, the BIIC will not output the RTO EV code in place of the RCR EV code following a retry timeout; however, the RTO bit in the BER will be set and an error interrupt will be generated if enabled.

Bits: 2:0 Name: RESERVED and zeros Type: RO

7-25

DIGITAL CONFIDENTIAL & PROPRIETARY

VAXBI REGISTERS 7.12 WRITE STATUS REGISTER

bb+2C

I

^O's

I

~!

~~~---Bit: 31 Bit: 30 Bit: 29 Bit: 28

GENERAL PURPOSE I'lEGIS"rE;:! 0 GENE;:!AL pURPOSE ~EGjS"rER 1 GENERAL PURPOSE REGIS;ER :1 GENERAL PURPOSE REGIS"rER 3

Name: General Purpose Type: WIC, DCLOC

Name: General Purpose Type: WIC, DCLOC

Name: General Purpose Type: W1C, DCLOC

Name: General Purpose Type: W1C, DCLOC

MI.O.oos .. ,

Register Register Register Register

3 (GPR3) 2 (GPR2) 1 (GPR1) 0 (GPRO)

Bits <31:28> when set indicate which general purpose registers have , been written to by a VAXBI transaction. The bit is set only if good

parity is received with the write data. ,~~

These bits are not set by loopback transactions.

Bits: 27:0 Name: RESERVED and zeros Type: RO

7-26

,-,.,

~__J

DIGITAL CONFIDENTIAL & PROPRIETARY Digital Internal Use Only

VAXBI REGISTERS 7.13 FORCE-BIT IPINTRISTOP COMMAND REGISTER

3' '615

be·30

1L..--_______ o·$ ___ ~~...;lyl---os----J1

C::lMMAND

Bits: 31:16

MAS,EP to ^ENABLE

Name: RESERVED and zeros Type: RO

Bits: 15:12 Name: Command (CMD) R/W, DC LOS Type:

C'

Indicates the 4-bi t transaction that is Only the IPINTR (HHHH)

into this field.

command code for either an IPINTR or STOP initiated by setting the IPINTRISTOP Force bit.

and STOP (HHLL) command codes should be loaded Bit: 11 Name: Master 10 Enable (MIDEN)

Type: R/W, DCLOS

Determines whether the master's 10 is transmitted on the BI 0<31:16> L

.'...-~"Jines during the CIA cycle of a transaction initiated by setting the

~/~PINTRISTOP Force bit. If the MIDEN bit is cleared, the BI 0<31:0> L lines remain deasserted during the CIA cycle. The MIDEN bit should be set to one when the Command field contains the IPINTR command code.

(The IPINTR transaction requires that the master's decoded 10 be transmitted on B1 0<31:16> L.) The MIDEN bit should be cleared when the Command field contains the STOP command code. (The STOP transaction requires that during the CIA cycle the BI 0<31:16> L lines be a RESERVED field and should not be driven.)

OBitS: 10:0 Name: RESERVED and zeros Type: RO

7-27

DIGITAL CONFIDENTIAL & PROPRIETARY

,

VAXBI REGISTERS

Dans le document System Reference Manual (Page 153-163)