~ RESERVED FIEI.D
CHAPTER 7 VAXBI REGISTERS
8.2 REQUIREMENTS ON NODES OF EACH CLASS
Section 8.2.1 specifies what transactions nodes
C
'~issue or respond to so that compatibility / compromi sed.of each class must of VAXBI nodes is not
C'
Section 8.2.2 then discusses those requirements by node class.
Section 8.2.3 discusses VAXBI requirements that relate to I/O space.
8.2.1 Required Sets of Transactions
The capabilities required of nodes of each class can be described by examining how nodes participate in transactions. Two distinct sets of transactions are involved. One set consists of transactions that rodes of one class must be able to respond to (MRS). The other set consists of transactions that nodes of a given class must be able to issue (MIS).
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DIGITAL CONFIDENTIAL & PROPRIETARY
Must Respond Set (MRS)
Digital Internal Use Only CLASSES OF VAXBI NODES
Suppose CI and C2 are two arbitrary node classes. If a node of class CI "may" issue transaction type TR to a node of class C2, then for the sake of compatibility all nodes of class C2 "must" respond to TR.
(For example, an adapter can issue quadword transactions to memories;
therefore, all memories must respond to quadword transactions.)
Consider all the types of transactions that nodes of class C2 must respond to. (In our example, for memories this would be transactions like the quadwbrd transactions.) This set of transactions is the Must Respond Set (MRS) for class C2. Nodes of class Cl MUST NOT depend on nodes of class C2 to respond to any transactions outside of MRS. (In terms of the example, had quadword transactions not been in MRS, adapters could not depend on all memory nodes to respond to quadword transactions. In this case, an adapter that issues quadword transactions to memory nodes might be incompatible with some memory nodes. )
Must Issue Set (MIS)
Suppose a node of class Cl "may" depend on receiving transactions of type TR from nodes of class C2i that is, a function of some nodes of class Cl cannot be exercised without the node receiving TR-type
f
transactions. Then all nodes of class C2 "must" be capable of issuing '-c~?i TR. (For example, adapters depend on processors to issue longword
transactions to I/O space; therefore, all processors must be capable of issuing longword transactions to I/O space.)
The set of transactions that nodes of class C2 must be capable of issuing is the Must Issue S~t (MIS) for class C2. Nodes of class Cl must not depend on receiving any transactions of any type outside of
MIS. (For example, processors must not depend on receiving INTR ~~
transacti ons, since INTR is not in the MIS of any node class.) ~..J The MRS and MIS for each of the three classes of nodes is shown in
Figure 8-1.
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C"
" )MUST RESPOND SET IMRS;
PROCESSOR PS
MEMORY MS
ADAPTER AS
DIGITAL CONFIDENTIAL & PROPRIETARY
I I I
Digital Internal Use Only CLASSES OF VAXBI NODES
MUS7 ;SSUE
SE-!MIS;
PM MM
AM
.... o.os,.
Figure 8-1: Required Sets of Transactions
Note that there is no simple relation between any MIS and any MRS.
For instance, quadword transfers are in the MRS of memories, but they are not in the MIS of processors or adapters. On the other hand, IPINTR is in the MIS of processors but not in the MRS of memories or adapters.
8.2.2 Requirements by Node Class
The rationale for why certain transactions are required for processor and memory nodes is given below.
( / Processo r Nodes
The required transactions for processor nodes are mainly the result of adapter design. Adapters communicate with processors and memories by means of memory accesses, processor accesses to adapter CSRs, and interrupts. To be compati~le with future processor designs, an adapter must issue to processors only those transactions which all processors can respond to, and must depend on receiving only those
(~,transactions which all processors can generate.
Processors must also cooperate to implement "indivisible" actions.
These indivisible actions are used to ensure the integrity of data structures that are updated by more than one VAXBI node, or by more than one process running on the same VAXBI node. The protocols that implement these actions must involve transactions that all processors can generate.
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DIGITAL CONFIDENTIAL & PROPRIETARY
Digital Internal Use Only CLASSES OF VAXBI NODES
As defined in Section 8.2.1, let PM (processor as master) and PS (processor as slave) be the MIS and MRS, respectively, for processors.* The following requirements dictate the contents of the PM and PS subsets. Processors must be able to:
o Generate all the appropriate accesses to any adapter's CSRs.
o Field interrupts from the adapter.
o Generate IPINTR transactions to signal processors and adapters that depend on this capability.
o Generate the IRCI and UWMCI transactions needed to implement indivisible actions.
The PM subset consists of:
o All longword data transfer transactions to I/O space, except:
(a) Only READ or RCI and only WRITE or WCI need be included.
(The data transfer transactions are READ, RCI, IRCI, WRITE, WCI, WMCI, and UWMCI.)
(b) Data transfer transactions to node private space are excluded from the PM subset.
word addressability is window space data word-accessible adapters processor.
required transfer
will be
for longword-Iength transactions, so
compatible with
node that the o IRCI and UWMCI transactions of anyone or more lengths, to memory space. The IRCI and UWMCI transactions implemented can be of different lengt~s.
o The, IDENT, IPINTR, and STOP transactions.
o
*For example, both the KA820 processor and the DB88 adapter must be able to issue the transactions in PM and respond to the transactions
in PS.
0
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