SYNCHRONOUS CONTROL SIGNALS

The VAXBI synchronous control signals include:

o BI NO ARB L o BI BSY L

o BI CNF<2:0> L

L _~\

I ~

BI NO ARB Land BI BSY L are the primary control signals on the VAXBI bus. The BI CNF<2:0> L lines carry confirmation codes that provide

"handshakes" between the master and slave nodes. f (~:

4-4

DIGITAL CONFIDENTIAL & PROPRIETARY Digital Internal Use Only

VAXBI SIGNALS

C

^4.2.1 BI NO ARB L (No Arbitration)

c

The BI NO ARB L signal is used to control access to the VAXBI data lines for arbitration. If BI NO ARB L is asserted in a given VAXBI cycle, then nodes may not arbitrate during the next VAXBI cycle.

Nodes monitor the BI NO ARB L signal so that data and command/address information do not contend with arbitration information.

The BI NO ARB L signal is asserted by the following:

o Nodes arbitrating for the bus during the arbitration cycle o The pending bus master from the cycle after i t wins the

arbitration until i t becomes bus master

o The bus master during the following cycles of its transaction:

Transaction Length Longword

Quadword Octaword

Cycles Imbedded ARB

Imbedded ARB and following cycle Imbedded ARB through the cycle after the second ACK data cycle

o The slave for all data cycles except the last

o All potential slaves for the third (decoded master ID) cycle of an IDENT command and for the IDENT arbitration cycle of an

IDENT command

o Nodes doing loopback transactions (see Section 4.2.3.2) o The bus master during its command/address cycle to prevent

arbitration from occurring, so i t can start another transaction following the current one. This mode operation, called "burst mode," is reserved for use Digital.

bus bus of by o Nodes during their power-up self-test, until the

registers can be accessed

VAXBI

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DIGITAL CONFIDENTIAL & PROPRIETARY

4.2.2 B1 BSY L (Busy)

VAXB1 SIGNALS

The B1 BSY L signal is used to provide the orderly transition of bus mastership from one node to another. Nodes monitor the B1 BSY L signal to determine the action that should be taken during the following cycle. The node that won the last arbitration may become bus master in the cycle following one in which i t detects the deasserted state of Bl BSY L (deassertion of Bl BSY L means a transaction has ended). The new master asserts BI BSY L on the first cycle of the new transaction.

The BIBSY L signal is asserted by the following:

o The bus master during the following cycles of its transaction:

Transaction Length Longword

Quadword Octaword

Cycles

Command/address, imbedded ARB

Command/address, imbedded ARB, and following cycle

Command/address, imbedded ARB through the cycle after the second ACK data cycle

o A node to delay the start of the next bus transaction until it is prepared to respond to another bus transaction. A timeout limits any node from extending Bl BSY L in this way for more ' than 127 consecutive cycles. Cycles of this type are referred to as "busy extension cycles." Nodes should not extend B1 BSY L for more than 16 consecutive cycles. (Section 10.2.1 explains these requirements.)

o The slave for all data cycles except the last

o Nodes doing loopback transactions (see Section 4.2.3.2)

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DIGITAL CONFIDENTIAL & PROPRIETARY Digital Internal Use Only

VAXBI SIGNALS

C

^4.2.3 Use of BI NO ARB Land BI BSY L

o

o

o

Figure 4-2 shows which nodes assert B1 NO ARB Land B1 BSY L during each cycle ofa transaction. Figure 4-3 shows the state sequences of B1 NO ARB Land BI BSY L that can occur.

CYCLE BI NO ARB L uset111d by:

Arbiultlnq Nooes Pendinq Muter Malter

51.".

91 BSY L - ' l i d by:

Arbitrating 1>;<>01lS

Pendinq Master Master Sla".

ARB C:A

I

I

I I

~

I

^ACl(

IA

I

^DATA

-

;

LAST LAST STALL ACK DATA DATA CIA

i~"1 i i

_•

V-i'-L

I 1

I .1

I

_•

I I

. I I I

Figure 4-2: Transaction Showing BI NO ARB Land B1 BSY L

4-7

DIGITAL CONFIDENTIAL & PROPRIETARY

C

G

COMMAND ADDRESS 10

SURST MODE COMMAND;

ADDRESS 00

A

VAXBI SIGNALS

ARB OR POWER-UP 01

PENDING MASTER 01

S

E

EXTENSION CYCl..ES WITHOUT PENDING MASTER 10

KEY:

SOn-! NO ARB;BSY LOW ASSERTED

Figure 4-3: State Sequences of BI NO ARB Land BI BSY L

4.2.3.1 Arbitration State - Figure 4-4 shows the state diagram for a node's arbitration control circuitry. Each state represents one bus cycle. The BI NO ARB L signal is asserted in all states except the idle state.

When in the idle state, a node waits for a request to transfer information over the bus. When a request is received, the node enters the arbitration cycle state as soon as the data lines are free, as indicated by a deasserted BI NO ARB L signal. The node then asserts the bit corresponding to its node ID in either the low-priority word or the high-priority word. The node compares the received data lines with the bit that it asserted. If the node is not the highest priority, it returns to the idle state and waits for the next arbitration cycle. If it is the highest priority, and if no bus

4-8

C·.·:

^..

o o

DIGITAL CONFIDENTIAL & PROPRIETARY Digital Internal Use Only

VAXBI SIGNALS

transaction is in progress (as indicated by a signal), i t enters the master state. If a bus progress, the node goes into the pending master the bus to become available.

deasserted BI BSY L transaction is in state and waits for During the first cycle of a node's bus transaction, the node is in the master state. The BI BSY L signal is asserted, along with the data and information lines that carry the command and address. Control is passed to the master control circuitry. The request condition is cleared during this state.

IDLE

b

NOARS&

I

^I

REO

Dans le document System Reference Manual (Page 63-68)