The Sigma 9 instructions are an extension of t.he Sigma 7 instruction set. This section describes the new instructions for Sigma 9 and also changes to Sigma 7 instructions.
2.1 .6.1 New Instructi ons for Si gma 9
There are three new instructions for the Sigma 9; they are: Load Real Address (LRA); Load Memory Status (LMS); and Load and Set (LAS).
Load Rea I Address loads into a general regi ster the rea I effecti ve address of the operand poi nted to by the instruction. The address loaded can be of a byte, halfword, word, or doubleword as de-termined by the setting of the condition codes at the beginning of execution. This means that the programmer can use LRA to obtain the real memory address of an operand under real, virtual, or rea I extended address i ng.
The Load Memory Status instruction is used to interrogate the status of a memory bank. It can also be used to perform a diagnostic action on a memory bank. The effective address of the instruction is used to determine whic h memory bank is to be referenced. The setting of the condition codes just prior to execution determines what diagnostic action is to be performed. The LMS instruction could be used, for example, to retrive under program control the contents of the memory snapshot registers. This feature may be used by the operating system for error logging or by a diagnostic program to assist in fault locating.
The Load and Set instruction will not have an immediate use on the Sigma 9. Load and Set is used in a multiprocessor system to prevent a given CPU from accessing a memory location already being used by another CPU. Load and Set will, however, have a definite use for Sigma 9 enhancements.
2.1.6.2 Modi fi ed Instructi ons
The extended capabilities of Sigma 9 have required the modification of some of the Sigma 7 in-structions. Most of the changes are concerned with the extended addressing capability of the Sigma 9. There are, however, totally new options available on some instructions.
Byte string instructions run five to six times faster on Sigma 9 when bytes are transferred on byte boundaries. Sigma 9 also has a speed advantage when bytes are transferred on word boundaries.
A new shift type instruction has been added. A number of applications require that a single bit marker be located within a word or doubleword filled with these markers. The new shift instruc-tion allows the programmer to perform a searching shift on either a word or doubleword to deter-mine the presence or absence of a particular bit or flag. The shift may be either left or right and will provide a count of the bits shifted while searching.
The floating point arithmetic on Sigma 9 is the same for Sigma 7 excep.t for the following dif-ference - the floating point is standard on Sigma 9 and is not an option. AIJ floating point instructions will yield identical results with Sigma 7.
Sigma 9 decimal operation differs from Sigma 7 in that Sigma 9 decimal instructions are much faster than Sigma 7 {2 to 3 times faster}. Also, Sigma 9 decimal instructions are capable of gen-erating either EBCDIC or ASCII preferred sign and zone codes. This option allows the programmer to choose the mode of operation most convenient for him.
The Read Direct and Write Direct instructions have had several important optional forms added to their formats. The Read Direct instruction is now capable of reading the snapshot register within the CPU. The information held in the snapshot register can be used for diagnostic purposes to dis-cover the nature of a fault in the CPU. The Read Direct instruction is now also capable of reading the state of the interrupt inhibits and sensing the various status of the individual interrupt levels within the CPU interrupt system. The ability to sense and record the status of individual inter-rupts becomes extremely useful when combined with a new feature of the Write Direct instruction.
This new feature of the Write Direct gives the programmer the ability to set the state of the inter-rupts {all states including active}. As an example, the programmer {using the Read Direct} may now sense and record the status of the interrupts and, at a later ti me (usi ng the Wri te Di rect)
re-estab-lish that same status in the interrupt system. The Write Direct instruction has also been modified to allow it to set the interrupt inhibits and to arm the snapshot feature. In arming the snapshot feature, the Write Direct supplies a clock counter and a condition select. The condition select describes what information is to be taken in the snapshot and the clock counter tells when it should be taken.
With one exception, the functions of the I/O instruction on Sigma 9 are identical with those on Sigma 7. The exception is a modification of the Halt I/O instruction that serves to generate a reset function for an entire lOP. This modification is called Reset I/O (RIO). RIO causes the se-lected lOP to generate an I/O reset signal to all devices attached to it. The use of several RIO instructions in sequence will cause the entire I/O system to be reset one lOP at a time. (Refer to Paragraph 2.3.1.4 for detai Is of I/O instructions.)