XDS AFC
UNIVAC 1106/1108 SYSTEM SUMMARY
• INTRODUCTION
The Univac 1108 was introduced in 1965 as a substantially improved version of the 1107. Modifi cati ons have been made to the 1108 si nce its announcement. These include multiprocessor capability (up to three processors); independent I/O proces-sors (lor 2 extended I/O controllers with up to 16 simultaneously active channels per 10C); bulk core availability; and (in mid 1969) the availability of the Exec 8 operating system. The 1108 is a very expensive but also very powerful 36-bit binary machine, primarily designed for the scientific marketplace.
The Univac 1106 (first announced in March 1969) is a slowed down version of the 1108, desi gned to extend the I ife and the market of the 1108. A CE can upgrade an 1106 to an 1108 in a matter of minutes. The 1106 is included in this study be-cause, with modular memory, its price/performance ratio places it mid-way between the Sigma 7 and the Sigma 9. Any references to the 1106 in this document apply hardware and software limitations make both machines very weak in time-sharing.
The 1106 with modular memory can handle four to six terminals; the 1108 with in-ternal I/O channels only (no 10C·s) can handle a maximum of 10 to 12 terminals and sti II process some batch or remote batch. With independent 10C·s, or with the shared processor system (announced in January 1970) wh i ch features an 1108 proces-sor dedicated to I/O handling, the time-sharing capabilities of the 1108 may be en-hanced. Unfortunately, theer is currently no information available on either of··
these latter two configurati ons.
Essential differences between the 1106/1108 are listed below:
Model
• UNIVAC 1106/1108 STRENGTHS
Multiprogramming: Exec 8 is a powerful multiprogramming system of the same class as IBM's OS/MVT.
It
handles a variable number of batch and re-mote batch jobs. Operator scheduling is kept to a minimum.Scientific Processing: The 1108, despite its age, is a very powerful machine in a strictly scientific environment.
Random Access Devices: The wide range of mass storage devices available must be considered a plus for Univac. However, software support for the re-movable disk pack is questionable at this time.
Application Packages: Univac has a wide range of scientific application packages avai lable.
• UNIVAC 1106/1108 WEAKNESSES
HARDWARE
The 1106/1108 represent a second generation architecture. They are not in-dustry compatible (6-bit character rather than 8-bit byte). The 1108 is a virtually obsolete machine; the 1106 was Univac's attempt to extend its life one or two more years.
Time-shari-ng is stri ctly an add-on to both the hardware and the software of the 1106/1108. Because of poor design, a very few terminals (4 to 6 on the 1106 - less than 15 on the 1108) will completely swamp the CPU. The reasons for this are the exceptional amount of operating system overhead and the cycle-stealing of the standard I/O channels. (The effects of the inde-pendent IOC's is not known. We have no reports of successful installations.) There is no critical real time hardware capability. Only one external inter-rupt level is avai lab Ie.
There is very poor storage utilization. The lack of a memory map requires excessive shuffling of core. Programs are typically large batch programs and language processors are not reentrant as on Sigma.
Some of the highlights of the Univac 1106/1108 hardware features include:
• MEMORY
Memory size ranges from 384K to 1.5M characters (6 bits/character) Cycle time 1.5l-lsec for the 1106
.75 I-lsec for the 1108
Access width is two words, one operand and one instruction if stored in dif-ferent modu I es.
The 1106 does not permit interleaving The 1108 can have 2-way i nterl eavi ng
• CPU
The 1106 has one port to memory
The 1108 can have up to 5 ports to memory
Memory protection is provided by two sets of Base and Limit registers, one for programs and one for data (thus permitting programs and data to be stored in different storage modu les to take advantage of Fetch execute overlap .
36-bit word
No decimal or byte string instructions
Fixed and floating point arithmetic is standard
Special processor modes permit operating on quarter, half or third of a word.
This is not the equivalent character addressing. There is no carry between the partial words.
Two sets of general registers (16 each), one reserved for the operating system and the other for the user plus 15 separate - user or system - accessible index registers.
Only 47 of the 128 total registers are program-accessible.
Overlap of operand fetch and next instruction is automatic if they are stored in different storage modules.
• INPUT/OUTPUT
I/O System: Integral I/O standard on both the 1106 and the 1108. Independ-ent I/O controllers (maximum 2) are optional on the 1108.
I/O capacity: Four to 16 simultaneous channels on the 1106. Eight to 16 simultaneous channels on the 1108. Each independent IOC on the 1108 can have 4 to 16 si mu Itaneous channe Is.
Standard integral I/O channels cycle-steal (and heavily) from the CPU.
The optional (and expensive) independent IOC's each have a se?Jrate port to . memory.
I/O bandwidth:
1106 standard channels 1108 standard channels 1108 externa I I/O
con-trollers
T ota I system bandwi dth:
333K words per second per channel. Total rate 667K words per second
440K words per second per channel. Total rate 1 .33M words per second
250K words per second per channel. Total rate 1 .33M words per second
11 06 - 667 K words per secon d 1108 - 1 .33M words per second
64 t<YV OR 384 K CHAR MINIMUM AND INCREMENTS
,....---,---r -- ----,- ---..,
1. 5 \JS CYCLE TIME I 1 1
FOR 72-B ITS 1 1 I
(DOUBLEWORD) 1 I 1
MAX MEMORY SIZE
1---...04-- _____
1 _ _ _ _ _ _ _ 1 _ _ _ _ _ _ ~256 I<:::N OR 1536 K I I 1
CHAR MEMORY ALSO '--_ _ -.--_ _ ~_ _ _ _ _ -L _ _ _ _ ~ _ _ _ _ --1
AVAILABLE IN SINGLE PORT
UNITIZED 256 t<YV TO MEMORY
SINGLE MODULE
MAX XFER RATE 667 I<YV OR 4 MCHAR PER SEC
INTEGRAL I/O CONTROLLER CENTRAL
5 1 6 1 7 I 8 PROCESSING
-r
L1.11.11
, - - - . U N,...--IT - - - - 'r - r - T - T - I - T - T - T - l
9110 111112113114 1151161 L_l.._..1._..l._ ..1._.L _...L_.l._.J
NOTES:
(1) THE INTEGRAL I/O CONTROLLER HAS 4,8, 12 OR 16 CHANNELS
(2) CHANNELS CAN DATA CHAIN
(3) ONE CHANNEL IS DEDICATED TO SYSTEM CONSOLE
UNIVAC 1106
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