•
•
Port number Interleave mode Bank size
• Memory unit number
• Memory un i t si ze
2.3 INPUT/OUTPUT SYSTEM
The input/output system for Sigma 9 represents major improvements over earlier Sigma I/O systems in throughput and flexibility. Two different types of input/output processors (lOpls) are available for use ina Sigma 9 system:
• Multiplexor lOP (MIOP) which controls up to 32 device controllers
• HIGH SPEED RAD lOP (HSRIOP) which controls up to four Model 7212 high speed RAD storage un i ts
The minimum Sigma 9 system configuration includes one MIOP. As many as 10 additional MIOP's and HSRIOP' s may be added to a monoprocessing system in any mix. In multiprocessing systems, the number of allowable 10P's in the system is reduced by the number of CPUls (maximum of four) added to the system. Since each processor (CPU or lOP) must have its own port to memory, a maximum of 12 processors can be configured in a Sigma 9 system.
In all systems, Homespace Bias is transmitted to the lOP from the controlling CPU during I/O in-struction execution. The Homespace Bias is added to the address values of X' 20' and X'211 for
CPU/lOP communication via core memory during the execution of I/O instructions.
2.3.1 MULTIPLEXOR lOP (MIOP)
The MIOP controls up to 32 device controllers in a dual-channel mode of operation similar to the earlier configuration of an MIOP with a bus-sharing lOP (BSMIOP). The MIOP has both 1-byte
(standard) and 4-byte (optional) interfaces. With the 4-byte option, the MIOP can operate in a
"burst" mode which causes the MIOP and a device controller to exchange complete records of data during a single service connection. This is similar to the operation of the earlier Selector lOP (SlOP), thus maximizing the throughput of a single device during times when data overruns on other devices are not probable. Transfer rates of an MIOP are typically 470 kb/sec on a 1-byte interface and 940 kb/sec on the optional 4-byte interface.
A unique memory-to-memory move option (MMM) allows the MIOP to move a maximum of 16K words
"from one areQ in core memory to another. Unlike similar operations using CPU instructions such as move. byte string (MBS),
MMM
is performed as an I/O operation which means the CPU does nothave to be tied up performing block movements of core memory data.
2.3.1.1
ChannelsThe MIOP is functionally divided into two separate operating channels, Channel A and B (ref-erence the following figure). Both channels can operate concurrently except for sharing the core memory bus (interface). I/O instructions provide for channel discrimination in their addressing scheme. Both channels are contained in a functional assembly called a Channel Control Unit (CCU), which provides the interface logic to core memory and the CPU's in the system. A third interface is provided for diagnostic uses and allows the lOP to be interrogated and controlled dur-ing preventive and corrective maintenance routines.
DATA, COMMANDS,
ADDRESS
Core Memory M(mory
~--/Busses
DATA,
COMMANDS, ADDRESS
CPU
MIOP
Channel A
Channel B
Subchannels
0-7
Subchannels
8-15
Subchannels16 -23
Subchannels0-7
~-CONTROL
ADDRESS
HOMESPACE BIAS CONDITION CODES INTERRUPT
' \ . PROCESSOR BUS
Multiplexor lOP - Functional Diagram
STANDARD
OPTION
OPTION
OPTION
Channel A - Channel A is standard in the MIOP and comes with eight subchannels (numbered 0- 7). Each subchannel controls one de vi ce controller. The basic set of ei ght subchannels can control both multi-unit device controllers (with up to 16 devices) and single unit device control-lers. Subchannels can be added in groups of eight to increase the number of channel A sub-channels to 8 - 15. The second increment adds subsub-channels 16 - 23. Subsub-channels numbered 8 - 23 can control only single unit device controllers. Subchannels 8 and 9 have special significance when the memory-to-memory move (MMM) option is installed.
Channel B - Channel B is an option which comes with eight subchannels. Channel B subchannels (numbered 0-7) can control both multi-unit device controllers (with up to 16 devices) and single unit device controllers. Thus, with both Channel A and Channel B installed, the MIOP can ac-commodate up to 32 device controllers. The ability of the Sigma 9 MIOP to control up to 16 multi-unit device controllers is an increase in flexibility over earlier 10piS where only eight multi-unit device controllers can be installed. Each subchannel has storage facilities (fast-access memory registers) in the MIOP to contain all the control parameters needed to operate a device controller. To improve accuracy and MIOP viabi
I
ity, parity generation/checking is performed on all subchannel storage registers.2.3.1.2 I/O Interface
Both channels come standard with a 1-byte interface which allows each device controller to ex-change a single byte of data every time it connects to the MIOP for service.
An optional 4-byte interface may be installed to each channel which then allows those device controllers that have similar interfaces to exchange up to four bytes of data every time it connects to the MIOP for service. Further, if the device controller is capable of exchanging more than four bytes during a service connection, it may initiate a IIburst modell operation and remain con-nected to the MIOP, exchanging data unti I zero byte count or channel end is encountered. The burst mode capability is available as part of the 4-byte option.
2.3.1.3 Memory-to-Memory Move (MMM)
A common requirement in efficient core memory management is the dynamic relocation of pro-grams and data wi thi n core memory. In the past it has been incumbent upon the CPU to perform this task of relocating blocks of data within core memory at the expense of increasing CPU over-head time and sacrificing valuable program execution time. With the MMM option, this task is transferred to the MIOP and is performed as a simulated I/O operation.
To accommodate this option, the MIOP must have the Channel A expansion option which provides subchannels 8 - 15. Subchannels 8 and 9 are dedicated to MMM when it is installed. The MMM option interfaces to subchannels 8 and 9 as I/O device controller simulators. Subchannel (device controller) 8 is used to specify the area in memory to which the data is to be moved (destination) and acts as an input device. Subchannel (device controller) 9 is used to specify the area in mem-ory from which the data is to be moved (source), and acts as an output device. The MMM is mech-anized within the MIOP and only transfers data on a word basis. Because all data transfers are ac-complished internal to the MIOP, the 4-byte interface option is not required. The MMM is con-trolled by I/O instructions addressed to Channel A, device controllers 8 and 9. The MMM trans-fers data at approximately 143K words per second (572 kb/sec).
2.3.1.4 I/O Instructions
The I/O instructions available for the Sigma 9 I/O system are as follows:
•
SIO - Start I/O•
TIO - Test I/O•
TDV - Test Device•
AIO - Acknowledge I/O•
HIO - Halt I/O•
RIO - Reset I/O•
POLP - Poll Processor•
POLR - Poll Processor and ResetThe instructions RIO, POLP, and POLR are new and consist of va;i:;':,Jns of the HIO instruction.
The 510, TIO, TDV, AIO, and HIO instructions operate as they did in Sigma
5/6/7
systems. To accommodate additional 10P's and to take advantage of the bus sharing feature of Channels A andB,
the format of I/O instructions has been modified as shown in the following figure. The AIO instruction format is essentially unchanged. The POLP and POLR instructions cause the addressed lOP to return fault status to a CPU general register and are usually executed as a result of a Processor Fault Interrupt (PFI).o
178 1112 14
2.3.1 .5 Ma i ntenance Interface
The Sigma 9 MIOP contains a maintenance interface which allows the MIOP to respond to Read Direct (RD) and Write Direct (WD) instructions executed by the CPU. The primary function of the maintenance interface is to enhance the maintainability of the MIOP by allowing the CPU to interrogate lOP internal control elements (via a snapshot register) and to single phase an lOP to analyze details of an I/O operation for diagnostic purposes.
2.3.1 .6 A I ternate Processor Bus
The Alternate Processor Bus option is a group of modules which provide an additional bus to con-nect lOP's and CPU's in the Sigma 9 system and enables lOP's to be partitioned in a multiprocessor system for di agnosti c purposes.
2.3.2 HIGH SPEED RAD lOP (HSRIOP)
The HSRIOP is a combination of an lOP and a device controller. Specifically, the field-proven designs of the Sigma 5/6/7 Selector lOP (SlOP) and the Model 7211 High Speed RAD controller have been integrated into a single unit now called the HSRIOP. The HSRIOP is solely dedicated for use with the existing Model 7212 High Speed RAD Storage Units. The HSRIOP may have as many as four Model 7212's connected to it with transfer rates up to 3MB per second. Each storage unit has a capacity of approximately 5.4MB.
2.3.2.1 Options
The only HSRIOP option is the Alternate Processor Bus described in Paragraph 2.3.1.6.
2.3.2.2 Mai ntenance Interface
The HSRIOP contains the same Maintenance Interface described in Paragraph 2.3.1.5.
2.3.2.3 I/O Instructions
The HSRIOP responds to the same I/O instructions described in Paragraph 2.3.1.4 except that it is not sensitive to channel addresses (bit 23 in the I/O instruction format).
2.3.2.4 I/O Operation
The HSRIOP and Model 7212 High Speed RAD Storage Unit always exchange data in the burst mode, and only one storage unit can be exchanging data with the HSRIOP at any given time.
2.4 CONFIGURATIONS
As mentioned earlier, user programs currently running on a Sigma 5, 6, or 7 are fully compatible with a Sigma 9 of equivalent or larger configuration. The RBM, BPM, and BTM operating systems will be modified so that they will also be compatible with Sigma 9. There will be, however, cer-tain minor differences in operating systems. These differences will be total~y transparent to the users and all discrepancies between hardware systems will be resolved by XDS's programming de-partment.