PRINCIPLES OF OPERATION AND HARDWARE DESCRIPTION
5.6 SELECTED UNIT CYLINDER INTERROGATION (SUCAR)
When a system is equipped with more than one RP02, it is often desirable to know the location of the
I
Figure 5-3 SU Cylinder Interrogation Circuit
5.7 ADDRESSING THE PACK (CAR, HAR, and SAR)
The RP02P Disk Pack consists of 11 evenly spaced recording platters mounted on a single shaft. Because of this precarious arrangement, the top- and bottom-most surfaces are not used for recording; instead, a metal disk is attached to the bottom surface. The disk contains 20 evenly spaced notches and a twenty-first notch called the Index.
A circuit, designed to detect these notches, rejects every other one of the twenty notches, thereby dividing the disk pack into ten equal sectors. These sectors are addressed by a 4-bit register called the Sector Address Register (SAR) (see Drawing RP15-0-30). The sector addresses are coded 00
8 through RP15-0-29). Head addresses are coded 00
8 through 23
8 through 3128 from the outer-most cylinder to the inner-most cylinder, respec-tively. Cylinders are addressed by an 8-bit register called the Cylinder Address Register (CAR) (see
Drawing RP15-0-28). When detected by the controller, illegal codes 313
8 through 3778 raise an error flag that results in the appropriate interrupts.
The intersection of a cylinder, head, and sector address defines a unique sector that is the smallest ad-dressable unit in the' system. Each sector has a data field of 128 36-bit words plus a header word that uniquely defines that sector. A word constitutes two PDP-15 data words during Read or Write opera-tions.
The decoding circuits for illegal cylinder, head, and sector addresses are shown in simplified form in Figure 5-4. Note that the AND gate that combines CAROO (1) with CAROl (1) enables all other inputs in the NECA equation; NECA must be a minimum of 3xx
8. This signal is then ANDed with CAR04 (1), CAR06 (1), and CAR07 (1) to produce an equation stating:
1 1 x x 1 x 1 CAROO (1)
--..J r )
CAROl (1) CAR04 (1)
CAR06 (1) ---~
CAR07 (1) _ _ _ _ _ _ _ - - - - J
is illegal.
This code includes the number 313
8 (among others). Note also that the conditions for the numbers 3148, 315
8, 316
8, and 3178 are decoded by the AND of the original equation [CAROO (1) and CAROl (l)J and CAR04 (1) with CAR05 (1).
1 1 x x 1 x x CAROO (1)
--..J r )
CAROl (1) CAR04 (1)
CAR05 (1)
---1
Two inputs remain which decode the numbers 320
8 to 337
8, inclusive, and all numbers equal to, or greater than, 340
8. They are:
1 1 x 1 x x x x CAROO (1)
~ j )
CAROl (1) CAR03 (1)
and
1 x x x x x CAROO (1)
+ j I
CAROl (1) CAR02 (1)
--- ... ---1
CAR 04 (1) H CAR 06 (1) H r -CAR 07 (1) H ----~J CAR 02 (1)
CAR 03 (1) H
--.---t-, .. ,/
CAR 04 (1) H ---1----..._
CAR 05 (1) H
-CAR 00 (1) L CAR 01 (1) L
HAR 01 (1) H
HAR 00 (1) H HAR 02 (1) H
"l{>-NECAH
NEHA H
NEHA L
NESA L
SAR 01 (1) H
-~ 1
-{>-
NESA HSAR 00 (1) H
SAR 02 (1) H ~
L _ _ _ _
Figure 5-4 Illegal Disk Address Decoding
1~-0449
In this way, coding covers all numbers from 313
8 to 377
8, inclusive, in the NECA equation. NEHA and NESA may be decoded in the same manner.
The Cylinder, Head, and Sector Address Registers comprise three incrementing ripple count registers formed from D-Type flip-flops. These registers are preset by DPLA ANDed with the corresponding lOB bit, and are cleared by CLR CAR, CLR HAR, and CLR SAR, respectively.
Control logic for the Cylinder, Head, and Sector Address Registers is shown on Drawings RP15-0-28, -29, and -30, respectively. Incrementing the SAR is initiated by signals called SECTOR END L (gene-rated after the completion of each sector) or MAl NT INC SAR L (see Figure 5-5). SECTOR END is con-ditioned by five signals: WEE (1), LEE (1), WCEE (1), TE (1), and NORMAL H. Any of the first four signals inhibits incrementing of the SAR if a word or longitudinal parity error was accumulated in a sector, or if a write check error or timing error occurred. The fifth signal inhibits incrementing of the SAR if the control is not in the NORMAL mode. When the controller is in the FORMAT mode, there-fore, the SAR is not used.
RP15- 0-30
CLR (B) L DPLA (B) L
WEE (1) L ---4:Jr-_ _ LEE (1) L
WCEE (I) L
TE (1) L ( ' ) 1
-CLEAR ~---~---~---~---~+1
~---~ ~----~
"'>O--+--C L R SA R L
-CRY L
NORMAL H
MAINT INC SAR L
+3V
CRY H
INC HAR
15-0450
Figure 5-5 SAR Control Logic
The actual incrementing of the SAR is inhibited if SAROO (1) and SAR03 (1) are both true. This condition produces a signal called CRY H (the NOT condition is shown in Figure 5-5) which indicates that the maximum SAR count has been reached (11
a). If this condition had been true prior to
SECTOR END, the data side of the synchronizing D-Type flip-flop would have been enabled and would have allowed this flip-flop to set at the leading edge of SECTOR END. This flip-flop then enables a pulse amplifier (M606) that generates a pulse at the trailing edge of SECTOR END. This pulse is ORed with CLR (B) Land DPLA (B) L to clear the SAR with CLR SAR L. The process just described allows the SAR to increment from the maximum code 11a to OOa.
If CRY H is true before SECTOR END, another decision is made. If the function being executed is not Read All or Write All, then INC HAR H is generated which, in turn, increments the HAR. Note that the SAR now counts from OOa to 11
a, and then always back to OOa. At the transition of 11a to OOa' the HAR is incremented providing the function is Read, Write, or Write Check.
The HAR is also incremented during Read All and Write All functions, but only when the SAR contains a count of lOa before SECTOR END. This is done by ANDing READ ALL + WRITE ALL H with SAROO
(1) Hand SAR03 (0) H 0
The HAR is shown in simplified form in Figure 5-6. Again, the maximum HAR count is decoded and used to disable incrementing of the HAR. The code is:
HAROO (1) H HAR03 (1) H HAR04 (1) H.
This is shown in Figure 5-6 in the NOT condition. In addition to disabling the HAR increment, this signal also enables the creation of INC CAR Land CLR HAR L. DPLA (B) Land CLR (B) L are also ORed to produce CLR HAR L.
Assuming that the maximum HAR count is not present, INC HAR H (generated on Drawing RP15-0-30) wi II produce the incrementing signal for HAR.
The CAR is shown in Figure 5-7. As with the SAR and HAR, the maximum CAR count is decoded and used to disable the incrementing of the CAR. The code is:
CAROO (1) H CAROl (1) H CAR04 (1) H CAR06 (1) H.
-INC CAR L
1 . . - _ - - - 1 +3 V
CLEAR
HAR 00 (0) L HAR 03 (0) L HAR 04 (0) L
HAR 00
INC HAR H
CLR(B)L DPLA (B) L
HAR 01 HAR 02
~---CLR HAR L
HAR 03 HAR 04 + 1
INC CAR H
INC CAR L
RP15-0- 29
15-0451
Figure 5-6 HAR, Simplified Schematic
RPI5-0-28
END OF PACK H
+3V
CLEAR
CAR 00 CAR 01 CAR 02
CAR 00 (0) L.--CJr--__
CAR 01 (0) L CAR 04 (0) L
CAR 06 (0) L--CI&-~"':
'x:l~ ... - CLR CAR L
CAR 03 CAR 04 CAR 05 CAR 06 CAR 07 t 1
END OF PACK H
~---4~-END OF PACK L
15-04112
Figure 5-7 CAR, Simplified Schematic
This is shown in the NOT condition in the figure. This code is also used to create END OF PACK H, a signal that indicates to the controller that the physical end of pack has been reached.
END OF PACK H is ORed with CLR (B) Land DPLA (B) L to produce CLR CAR L.
Assuming that the maximum CAR count is not present, INC CAR H (created on Drawing RP15-0-29) will produce the signal necessary to increment the CAR.
The CAR, HAR, and SAR are shown functionally in Figure 5-1. Note the connection between the CAR and the INT & STATUS CONTROL box. This connection represents END OF PACK.
5.S CYLINDER COMPARISON
The RP15 Cylinder Comparator is shown in Drawing RP15-0-27 and in simplified form in Figure 5-S.
The Cylinder Comparator maintains a check between the controller Cylinder Address Register and the Selected Unit Cyl inder Address Register. This logi c is used to determine if the Seek state should be entered. Each state of every CAR bit is ANDed with the opposite state of the same SUCAR bit. Each AND is ORed to one composite OR that issues -CYL CMPR L until all bits correspond. If CYL CMPR H is true, reading or writing proceeds and the Seek state is not entered. This is described in more detail in Major State Control, Paragraph 5. 14.
CAR 00 (1) H SU CAR 00 (0) H CAR 00 (0) H
S U CAR 00 (1) H - CYL CMPR H
• •
• •
-CYL CMPR L• •
• •
•
CAR 07 (I) H SU CAR 07 (0) H CAR 07 (0) H
SU CAR 07 (I) H RP15-0-27
15-0453
Figure 5-S Cylinder Comparator, Simplified Schematic