REGISTER ADDR BANK DESCRIPTION

TCON 4 2 Timer control register. Controls operation and configuration of Timers 1 and 2 and compare and capture subsystems.

CMPRO 0 3 Compare registers. Contents of compare registers CMPR1 1 3 are constantly being compared with Timer 1 or CMPR2 2 3 Timer 2. When anyone of the compare registers CMPR3 3 3 matches the timer, it generates an action specified CMPR4 4 3 by an action register. In the PWM mode, a match with CMPR5 5 3 timer resets the corresponding CMPx pin to a low

level.

ACTO 0 4 Action registers. Contents of action registers ACT1 1 4 determine what action should take place on the ACT2 2 4 CMPx pin when the compare registers match the ACT3 3 4 timer, including generation of an interrupt. In ACT4 4 4 the PWM mode, the action registers act as double ACT5 5 4 buffers for the corresponding CMPRx register.

TCON10

ACTO

TCON 9 !C SET J

0 ^Q CMPO

I-

'"

II:

'"

Il.

16 :::E 0 RESET

K CLR

(.)

ACTO

ACT1 ACT5 ACTO

•

CMPINTO

CMPINT1

ACTO ^{r--_ _} -+-_CMP1-CMP3

I

::~{ ~. ---+-_~:::I

. TCON12 PINS

TO CAPTURE SUBSYSTEM

Figure 3-21. Compare Module

The compare registers are used to store certain values or periods. These are compared with timer values. Bits 8 through 12 of the timer control (TeON) register control the operation of the compare registers. Figure 3-22 and Table 3-12 show the functions of the TeON register bits,

15 14 13 12 11 10 9 8· ⁷ 6 5 4 3 2 0

COMPARE I

CONTROL I ^TIMER2

ot

CAPTURE I. ^{CONTROL . CONTROL}

CONTROL I

NOTE: t Reserved bit. Should be cleared to

o.

Figure 3-22. TCON Register Compare Bit Configuration

Architecture - Event Manager

Table 3-12. TCON Compare Register Description

BIT# DESCRIPTION compare interrupts are disabled.

1 = Enables the compare subsystem. Allows normal operation of compare subsystems.

9 Timer select for Compare subsystem. Set to zero on reset.

3.7.1.1 Compare Registers

Once a value is stored in each of the six compare registers, the compare system works independently without any intervention from the CPU. Each of the compare registers (CMPRO through CMPR5) is constantly comparing itself with either TMR1 or TMR2.

When a match is detected between the value stored in the compare register and the value in the timer, a match signal enables the corresponding action register to carry out an action on a compare output pin. All compare registers have the same bank address of 3h, and port addresses of Oh through 5h. They of timer matches compare register value), each of the compare output pins can either be set high, reset low, or toggled. In addition, each action register can specify generation of one or both interrupts (CMPINTO AND CMPINT1).

Figure 3-23 shows the configuration of the bits in each action register.

15 14 13 12 11 10 9 8 7 6 5 4 3 2

o

1 CMPO 1 CMP1 1 CMP21 CMP31 CMP41 CMP51 CMPINTO CMPINT1 Reserved ·1 Figure 3-23. ACTx Register Configuration

Bits 4 through 15 of the action register control (in pairs) the action of CMPO through CMP5. Bits 2 and 3 control generation of CMPINTO and CMPINT1.

Bits 0. and 1 are reserved. ACTO through ACT5 have the same bank address of 4h and port addresses Oh through 5h. They can be read from or written to using these addresses.

When the value in the specified timer equals the value in a compare register, the corresponding action register will specify an action depending upon the configuration as shown in Table 3-13.

Table 3-13. Action Register Description BIT # FUNCTION DESCRIPTION 15,14 Set/Reset 00 = No action taken on pin CM PO.

CMPO 01 = Resets pin CMPO to a low level.

10 = Sets pin CM PO to a high level.

11 = Toggle pin CMPO.

13,12 Set/Reset 00 = No action taken on pin CM Pl.

CMPl 01 = Resets pin CMPl to a low level.

10 = Sets pin CMPl to a high level.

11 = Toggle pin CMP1.

11,10 Set/Reset 00 = No action taken on pin CMP2.

CMP2 01 = Resets pin CMP2 to a low level.

10 = Sets pin CM P2 to a high level.

11 = Toggle pin CMP2.

9,8 Set/Reset 00 = No action taken on pin CM P03.

CMP3 01 = Resets pin CMP3 to a low level.

10 = Sets pin CMP3 to a high level.

11 = Toggle pin CMP3.

7,6 Set/Reset 00 = No action taken on pin CMP4.

CMP4 01 = Resets pin CMP4 to a low level.

10 = Sets pin CMP4 to a high level.

11 = Toggle pin CMP4.

5,4 Set/Reset 00 = No action taken on pin CMP5.

CMP5 01 = Resets pin CM P5 to a low level.

10 = Sets pin CM P5 to a high level.

11 = Toggle pin CMP5.

3 Set CMPINTO

o

1 = Generates interrupt and sets bit 6 in I F register.

2 Set CMPINT1

o

1 = Generates interrupt and sets bit 7 in I F register 1 Reserved Should be set to 1.

0 Reserved Should be set to 1.

Architecture - Event Manager

3.7.7.3 Compare pins

There are four output pins (CMPO through CMP3), dedicated to the compare subsystem. Two additional pins are also available for the compare subsystem.

These pins (CMP4/CAP2 and CMP5/CAP3) are shared with the capture (in-put) subsystem. CMP4/CAP2 and CMP5/CAP3 are configured by bits 11 and 12 of the TCON register. Each of the compare output pins can be con-trolled by all six action registers to create specific waveforms. However, if two action registers specify simultaneous action (i.e., set is specified by one action register, while toggle is specified by other action register), unpredictable ac-tion can occur. Pins CM PO through CM P3 are set low on reset. Pins CMP4/CAP2 and CMP5/CAP3 are configured as inputs and put in a high impedance at reset.

3.7.7.4 Compare Interrupts

Bits 2 and 3 of each action register can generate interrupts (CMPINTO and CMPINT1) to the CPU, when the corresponding compare register generates a match or EQ signal. CMPINTO sets bit 6 in the interrupt flag register (IF).

CMPINT1 sets bit 7 of IF. Both interrupts can be masked by using the inter-rupt mask register (1M).

3.7.7.5 High Precision PWM Mode

The compare subsystem has a mode for generating high precision pulse width modulation (PWM) outputs (refer to Figure 3~24). In the high precision mode, the pulse width on pins CMPx has two extra bits of resolution. Thus, the pulse width in this mode can be specified with a minimum resolution of 40 ns @ 25.6 Mhz (vs 160 ns in the normal compare mode). Table 3-14 gives a comparison between the high precision PWM mode and the normal compare mode.

TMR RESET

TCON8-r-.---~

TCON9

ClKIN

INTERNAL DATA

BUS

WR ACTx

ClKIN J

K

Figure 3-24. Compare Subsystem in PWM Mode

Table 3-14. PWM Resolution Bits Comparison

PWM Bits of Resolution

Frequency Normal Compare High Precision

(in KHz) Mode PWM Mode

100 6 8

25 8 10

6.26 10 12

1.506 12 14