Memory Organization

The TMS320C14/E14 devices utilize a modified Harvard architecture with two separate spaces for data and program storage. The TMS320C14 contains 256 words of RAM for data and 4K words of ROM program space. The TMS320E14 contains 256 words of RAM for data and 4K words of EPROM program space. As mentioned in section 3.2.2, internal or external program memory space may be accessed by the CPU, depending on the mode the CPU is operating in. Mode changing, which is both hardware and software

con-troabe' effectively doubles the amount of program memory, allowing the processor to perform multiple tasks.

3.4.1 Data Memory

The TMS320C14/E14 devices contain a 256-word x 16-bit RAM area for data storage. Figure 3-10 shows the memory map for the data RAM. The data RAM may be considered as 256 registers for temporary storage/fast access for data.

DATA I/O

O(OOOOh) (0000< 10

1

EXTERNAL 7(>0007)

PAGE 0

127(007Fh) 128(0080h)

PAGE 1

256(00FFh)

Figure 3-10. Data Memory Map

Architecture - Memory Organization

3.4.2 Program Memory

OOOO(OOOh)

3999(F9Fh) 4000(FAOh) 4015(FFFh)

C-14 ON-CHIP E-14 ON-CHIP EXTERNAL

ROM EPROM MEMORY

OOOO(OOOh) OOOO(OOOh)

AVAILABLE AVAILABLE AVAILABLE

MEMORY MEMORY MEMORY

SPACE SPACE SPACE

4088(FF8h)

RESERVED I/O PORT 0-7

4095(FFFh) 4095(FFFh)

MC/MP = 1 MC/MP=1 MC/MP=O

Figure 3-11. Program Memory Map

Figure 3-11 shows options for program memory storage. Aside from an on-chip program 4K-word x 16-bit ROM or EPROM, the TMS320C14/E14 can access external memory as well. The selection of memory resource is done with the MC/MP bit found as part of the SYSCON register. As stated in Section 3.2.2, setting this bit high configures the device to select the on-chip resource (ROM or EPROM). Setting this bit low configures the device to se-lect the off-chip memory device. This device is initialized at reset when the NMI/MC/MP pin is sampled, .and may be subsequently altered through writes to the SYSCON register. This ability to alter the MC/MP bit at run time yields a mechanism to easily expand program memory beyond 4K-words up to a maximum of 8K-words. Note that the upper eight words of external memory are reserved for external I/O ports 0 through 7.

It should also be noted, that the TMS320E14 includes a security bit which, when set, denies read access to the EPROM. Finally, the last 96 words in the ROM on the TMS320C14 are reserved for Texas Instruments internal use.

3.4.3 Auxiliary Registers

The TMS320C14/E14 devices provide two 16-bit auxiliary registers (ARO and AR1). This section discusses each register's function and how an auxiliary register is selected, loaded, and stored.

The auxiliary registers may be used for indirect addressing of data memory, temporary data storage, and loop control. Indirect addressing allows place-ment of the data memory address of an instruction operand into the least-significant eight bits of an auxiliary register. The registers are selected by a single-bit Auxiliary Register Pointer (ARP) that is loaded with a value of 0 or 1, designating ARO or AR1, respectively. The ARP is part of the status register, and can be stored in memory.

When the auxiliary registers are autoincremented/decremented by an indirect addressing instruction or by the BANZ (branch on auxiliary register not zero) instruction, the lowest nine bits are affected (see Figure 3-12). The auxiliary registers are useful as counters when the BANZ instruction is used. This counter portion of an auxiliary register is a 9-bit counter, as shown in Figure 3-13 and Figure 3-14.

I COUNTER

:. ..

I I

15 ~I§ 7

j

AR

I ^! I

INDIRECT ADDRESS

.

Figure 3-12. Auxiliary Register Counter

15 8

AR UNAFFECTED 1 1 1 1 1 1 1 1 1 INCREMENT

15 8

AR UNAFFECTED 0 0 0 0 0 0 0 0 0

Figure 3-13. Indirect Addressing Autoincrement

15 8

AR UNAFFECTED 1 1 1 1 1 1 1 1 1

DECREMENT

15 8 0

AR UNAFFECTED o 0 0 0 0 0 0 0 0

Figure 3-14. Indirect Addressing Autodecrement

Architecture - Memory Organization

The upper seven bits of an auxiliary register (Le., bits 9 through 15) are unaf-fected by any autoincrement/decrement operation. This includes autoincre-ment of 111111111 (the lowest nine bits go to 0) and autodecreautoincre-ment of 000000000 (the lowest nine bits go to 111111111); in each case, bits 9 through 15 are unaffected.

The auxiliary registers can be saved in and loaded from data memory with the .SAR (store auxiliary register) and LAR (load auxiliary register) instructions.

This is useful for performing oontext saves. SAR and LAR transfer entire 16-bit values to and from the auxiliary registers even though indirect addressing and loop counting utilize only a portion of the auxiliary register. See Section 4 for programming of the indirect addressing mode.

The BANZ instruction permits the auxiliary registers to also be used as loop counters. BANZ checks if an auxiliary register is zero. If not, it decrements and branches. See Section 5.3.3 for loop code using the auxiliary registers.

3.4.4 Memory Addressing Modes

The TMS320C14/E14 can address up to 4K words of program memory and up to 256 words of data memory. Three forms of instruction operand ad-dressing can be used: direct, indirect, and immediate adad-dressing. Figure 3-15 illustrates operand addressing in the three modes. The addressing .modes are described in detail in Section 4.1.

INSTRUCTION DIRECT ADDRESSING IOPCODEI dma ] DP

~~7/~7--l~)A~.1LI~::=O:P:E=RA=N=D=:::

INSTRUCTION INDIRECT ADDRESSING I OPCODE I ARP

~---~·1LI ^__ ~A~R~(A~R~P)~~~~ ^__ O_P_E_RA_N_D __ ~

INSTRUCTION IMMEDIATE OPERAND I OPCODE IOPERAND\

Figure 3-15. Methods of Instruction Operand Addressing

In the direct addressing mode, the 1-bit data memory page pointer (Of» se-lects either page 0 consisting of memory locations 0-127 or page 1 consisting of locations 128-255. The data memory address (dma), specified by the seven LSBs of the instruction concatenated with the OP, addresses the desired word within the page. Note that OP is part of the status register and thus can be stored in data memory.

Indirect addressing uses the lower eight bits of the auxiliary registers as the data memory address. This is sufficient to address all 256 data words; no paging is necessary with indirect addressing. The current auxiliary register is selected by the auxiliary register pointer (ARP). In addition, the auxiliary registers can be made to autoincrement/decrement during any given indirect

instruction. Note that the increment/decrement occurs after the current in-struction is finished executing.

When an immediate operand is used, it is contained within the instruction word itself.

Architecture - Bit Selectable I/O Port