The M37720S1 FP has a 4-bit, 2-channel real-time output function which is shared with port P6 as the output port. As with the other ports, the port P6 direction register is in the input state after resetting and therefore functions as a regu-lar 1/0 port. To use the real-time output function, be sure to underflow occurrence, the previously written data are output.
16-BIT CMOS MICROCOMPUTER
Address Real-time output control register
Real-time output 0 validity bit
o :
Invalid1 : Valid
~--- Real-time output 1 validity bit
o :
Invalid 1 : Valid62,.
Fig.78 Real-time output control register bit configuration
Address
Fig.79 Pulse output data register bit configuration
D
Fig.~~ Real-time output block. diagram
D=F/F
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2-153, .~ ,
WATCHDOG TIMER
The watqhdog timer is used to detect lJn.expected execu-tion sequence caused by software run-away. Figure 81 . shows a block diagram of the watchdog timer.
The watchdog timer consists of a 12-bit binary counter.
The watchdog timer counts the clock frequency divided by 32 (h2) or by 512 (f512 ). Whether to count fs2 or f512 is de-termined by the watchdog timer frequency selection flag shown in Figure 82. f512 is selected when the flag is "0" and 132 is selected when it is "1 ". The flag is cleared after reset.
FFF'6 is set in the watchdog timer when "L" or 2Vee is ap-plied to the RESET pirr, STP instruction Is executed, data is written to the watchdog timer, or the most significant bit of the watchdog timer become "0".
After FFF'6 is set in the watchdog timer, the contents of watchdog timer is decremented by one at every cycle of selected frequency f32 or f512' and after 2048 counts, the most significant bit of watchdog timer become "0", and a )Vatchdog timer interrupt request bit is set, and FFF'6 is preset in the watchdog timer.
Normally, a program is written so that data is written in the watchdog timer before the most significant bit of the watch-dog timer become "0". If this routine is not executed ~ue to unexpected program execution, the most significant bit of the watchdog timer become eventually "0" and an interrupt is generated.
The processor can .be reset by setting the bit 3 (software reset bit) of processor mode register described in Figure 10 in the interrupt section and generating a reset pulse.
The watchdog timer stops its function when the .RESET pin voltage is raised to double the Vee voltage.
The watchdog timer can also be used to recover from when the clock is stopped by the STP instruction. Refer t6 the section on clock generation circuit for more details.
The watchdog timer is also in the hold state during hold, DMA transfer, or refresh. Therefore, the input to the watch-dog timer is prohibited.
MITSUBISHI MICROCOMPUTERS
M37720S1FP,M37720S1AFP
16-BIT CMOS MICROCOMPUTER
Watchdog timer Irequency selection
(connection lorced to 132 during STP instruction execution) 132 - - 0
f512 --0
Hold Write to watchdog timer
Fig.81 Watchdog timer block diagram
Set FFF1~
Address
7 6 5 4 3 2 1 0 61
I.
·F:[XJ"'""'Xl>¢<:"'"':>~~""l'I':rx'""?lIXo:"'"":>I':N:-?II"""""1) :~!~~~~gfl~;er Irequency
L
0 : Select1",
1 : Select 132
Fig.82 Watchdog timer frequency selection flag
RESET CIRCUIT
16-BIT CMOS MICROCOMPUTER
contents of address FFFF,6 • and A7 - Ao to the contents of address FFFE,6.
Figure 83 shows the status of the internal registers when a reset occurs.
(3i) A·O conversion interrupt control register (70,.)'"
l><JXlXI)<J
0 10 01 0 1 (39) UART 0 Iransmission interrupt control register (71,.)···lXIXIXIXl 0 0 010 (40) UARTO receive interrupt control register (72,.)'"l><JXlXI)<J
0 0 010 (41) UART1 transmissioo interrupt cootrol register (73,.)'"lXIXIXIXl
0 0 0 0(4i) Timer BO interrupt control register (7A,.)···1XlXIXlIXl 0 010 01
~9) Timer Bl interrupt control register (7B,.)···1XlXIXlIXl 0 010 01 (6t) DMA2 control register (1 FEE,.)'"
lXlXlolololololol
(63) DMA3 mode register L (lFFC,.)'" I DO,.
I (64) DMA3 mode register,H (lFFO,.),,' I
00,.
I (65) DMA3 control register (tFFE,.),··
IXlXl
0 I 0 I 0 I 0 I 0 I 0 I~9) Watchdog timer frequency selection flog (SI,.) .•.
1XIXlXt><[><lx1 a I
(66) Processor status register PS 1010101?1?1 0 1010Ill?I?1~O) Real-time output control register (S2,.) .. ·IXIXIXIXIXIXI 0 I 0 I (61) Program bank register PG I' DO;.
Flg.83 Microcomputer Internal status during reset
2-155
Figure 84 shows an example of a reset circuit. The reset in-put voltage must be held O.9V or lower when the power vol-tage reaches 4.5V.
M37720S1FP
~poweron
ov ov
Fi9.84 Example of a reset circuit (perform careful evaluation at the system design before using)
MITSUBISHI MICROCOMPUTERS
M37720S1FP,M37720S1AFP
16·BIT CMOS MICROCOMPUTER
INPUT/OUTPUT PINS
Ports P10 to P4 all have a data direction register and each bit can be programmed for input or output. A pin becomes an output pin when the corresponding data direction regis-ter is set and an input pin when it is cleared.
When pin programmed for output, the data is written to the port latch and it is output to the output pin. When a pin is programmed for output, the contents of the port latch is read instead of the value of the pin. Therefore, a previously output value can be read correctly even when the output
"L" voltage is raised due to reasons such as directly driving an LED.
A pin programmed for input is floating and the value input to the pin can be read. When a pin is programmed for in-put, the data is written only in the port latch and the pin stays floating.
If an input/output pin is not used as an output port, clear the bit of the corresponding data direction register so that the pin become input mode.
Figure 85 presents the port P10 to port P4 block diagrams and E pin output format.
In the evaluation chip mode, port P4 is also used as the control signal terminal. Refer to the section on evaluation chip mode for more details.
2-156
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MITSUBISHI MICROCOMPUTERS
M37720S1FP,M37720S1AFP
16-BIT CMOS MICROCOMPUTER
• Ports P83' P87, P9s, P94, P92, P90, P107, P10s, P10s, P104 (Inside dotted-line not included) Ports P54' P52, p50'( Inside dotted-line included)
Data bus
,..j Direction registert
O~~~~r<
....
A-0---1 Port latch
1 1
'" j-A--h
I~ ,
L _____ ...J
• Ports P4s-P43 (Inside dotted-line not included)
Ports P47, P57, P56, P5s, P53, P51, P86, P82' P97' P9s, P93, P91, P102, P101, P100 (Inside dotted-line included.
Data bus
• Ports P67 - P60
but P82 and P86 are without hysterisis)
r - - - - -;
L _____
J
• Ports Pls-P7o(lnside dotted-line not included) Port P77 (Inside dotted-line included)
Data bus
Analog input
r - - - - --, I
I I
L _ _ _ _ _ .J
• Ports P85 • P84 • P8,. P80
Data bus
• Port P103
Direction
register\-Data bus
A
.... O"'~~
-
H
Port lalchI- - • ro
• 1,
A
"'"
Fig.8S Block diagram for ports P10 to P4 in microprocessor mode and the E pin output
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2-157MITSUBISHI MICROCOMPUTERS
M37720S1FP,M37720S1AFP
16-BIT CMOS MICROCOMPUTER
PROCESSOR MODE BYTE pin
Either the microprocessor ,mode or evaluation chip mode is selected in accordance with the contents of bit 0 of the processor mode register shown in Figure 86. Bit 1 must al-ways be set to 1.
When accessing the external memory, the level of the BYTE pin is used to determine whether to use the data bus as 8-bit width or 16-bit width.
The data bus width is 8 bits when the level of the BYTE pin is "H".
Figure 87 shows the port P4, A7/MA7 to AD/MAD, A15/D15 to As/Ds, A23/D7 to A16/Do, R/W, BHE, BLE, ALE,RDY, HOLD, and
q,
1 functions in the two different processor modes.The data bus width is 16 bits when the level of the BYTE pin is "L".
The external memory area varies with the mode. Figure 88 presents the memory map in each processor mode., When the external memory is to be accessed, it is influenced by the BYTE pin and processor mode register bit 2( wait bit) as explained below.
When accessing the internal memory, the data bus width is always 16 bits regardless of the BYTE pin level.
Fig.86
2-158
7
I 1 1 1 1 1 11
I I
,
Address Processor mode register 5E'6
Processor mode bit : Microprocessor mode 1 : Evaluation chip mode
Wait bit
o :
Wait1 : No wait
Software reset bit
Reset occurs when this bit is set to "1"
Interrupt priority resolusion time selection bit 00 : Select 1/f(X,N)X14
o
1 : Select 1/f(X'N)X8 1 0 : Select 1/f(X'N)X4Test mode bit This bit must be "0"
Stack bank selection bit
o : Bank 016 1 .: Bank FF16 Processor mode register bit configuration
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MITSUBISHI MICROCOMPUTERS
M37720S1FP,M37720S1AFP
16-BIT CMOS MICROCOMPUTER
r--
CMt 1 1----
CMO 0 1Port
~
Microprocessor mode Evaluation chip modeE
I
r-Access except DRAM A,/MA, Same as left
A,IMA, -Ao/MAo
:::x
Address A,-Aox::
\
Ao/MAo E
~
Access DRAM A,/MA,
-
Same as left-Ao/MAe X Address AAddressX - 1RowT iCo'iu;;;;;j~
A'5- A•
I I
E BYTE="L"
A15/ D15
~
Same as le(t- A./D,
Qgd_
A15/ D15
I E
I r
E A15-A.1I""
As/D.
A15/ D15
-:J\
Address A.-A15C
As/D.~
BYTE="H" -A./D. ... A15/D15
(odd)
Port P4, P5 and their direction registers are treated as t6-bit bus width_
E A'3-A,.!
r
BYTE="L"
A'3/ D,
~
Same as left-A,./Do (even)
A23ID,
A23-A,.1
I
E A'3 A,. !I "
\ BYTE="H" E
A,.lDe
A23/D, -A,./Do
~
(even, odd) A23/MA, -A,./Do~
(even, odd)Same as for A,5/D,5-A./D.
ALE E~