MITSUBISHI ~mm~
~ SEMICONDUCTORS U(!J(!J U
~ SINGLE-CHIP 16-BITI Enlarged
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MICROCOMPUTERS edition
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MITSUBISHI ~.:.;'
ffi.·.\."'.'Ir.'·,·'.·.· ..•. •.~.~.".!O.·.·:'.:;.·.',~.· 'I.l
SEMICONDUCTORS B~i!J I
SINGLE-CHIP 16-BIT Enlarged
MICROCOMPUTERS edition
All values shown in this catalogue are subject to change for prod- uct improvement.
The information, diagrams and all other data included herein are, believed to be correct and reliable. However, no responsibil- ity is assumed by Mitsubishi Electric Corporation for their use, nor for any infringements of patents or other rights belonging to third parties which may result from their use.
'0
GUIDANCE
MELPS 7700 16-81T MICROCOMPUTERS
PROGRAMMABL E ROM MICROCOMPUTERS
APPENDICES
MITSUBISHI MICROCOMPUTERS
INDEX
DGUIDANCE
PAGEIndex by Function ... '''1-3 Development Support Systems ... ·· .. · .. · .. · ... · ... · .... · ... · .... · .. · ... · ... 1 ~6
Ordering Information··· .... ··· .. ···· .. ··· .. ··· .. ··· .. ··· '1-8 Package Outlines· .. · .. ··· .. ·· .. ··· .. ··· .. ··· .. · ... ·· .. ··· .. ··· '1-9 letter Symbols for The Dynamic Parameters ... · .. · .. · ... ·1-12 Symbology .. ··· .. ··· .. ··· .. ··· .. ··· .. ··· .. ··· .. ··· .. ···· ... '1-15 Quality Assurance and Reliability Testing .... · .. · .. · ... · ... · ... · .. · .. · ... · ... · ... "1-18 Precaution in Handing MOS IC/lSls ... '1-24
UMELPS 7700 16-BIT MICROCOMPUTERS
M37702M2-XXXFP, M37702M2AXXXFP, M37702M2BXXXFP, M37702S1 FP, M37702S1AFP, M37702S1 BFP Single-Chip 16-8it CMOS Microcomputer .. · ... · .. ·2-3 M37702M4-XXXFP, M37702M4AXXXFP, M37702M4BXXXFP, M37702S4FP, M37702S4AFP, M37702S4BFP
Single-Chip 16-8it CMOS Microcomputer .. · ... · .. ·2-62 M37703M2-XXXSP, M37703M2AXXXSP, M37703M2BXXXSP, M37703S1SP, M37703S1ASP, M37703S1BSP
Single-Chip 16-8it CMOS Microcomputer' ... '2-65 M37703M4-XXXSP, M37703M4AXXXSP, M37703M4BXXXSP, M37703S4SP, M37703S4ASP, M37703S4BSP
Single-Chip 16-8it CMOS Microcomputer ... 2-84 M37720S1 FP, M37720S1AFP 16-8it CMOS Microcomputer··· .... ·· ... ··· .. ·· .. ··· .. ··2-86 M37730S2FP, M37730S2AFP, M37730S2BFP, M37730S2SP, M37730S2ASP, M37730S2BSP
16-8it CMOS Microcomputer· .... ···· .. · .. ··· .. · .. ··· .. ·· .. ··· .. ··· .. ·2-179 M37732S4FP, M37732S4AFP, M37732S4BFP
16-8it CMOS Microcomputer· .. ··· .. ··· .. ··· .. ··· .. ··· .. ·2-237 MElPS 7700 Addressing Modes ... ···· .. ··2-298 MElPS 7700 Instruction Code Table ... ···2-341 MElPS '7700 Machine Instructions··· .. ··· ... ···· .. ··2-344
II PROGRAMMABLE ROM MICROCOMPUTERS
M37702E2-XXXFP, M37702E2AXXXFP, M37702E2BXXXFP, M37702E2FS, M37702E2AFS, M37702E2BFS PROM Version of M37702M2-XXXFP, M37702M2AXXXFP, M37702M28XXXFP .... ·3-3 M37702E4-XXXFP, M37702E4AXXXFP, M37702E4BXXXFP, M37702E4FS, M37702E4AFS, M37702E4BFS
PROM Version of M37702M4-XXXFP. M37702M4AXXXFP, M37702M48XXXFP .... ·3-26 M37703E2-XXXSP, M37703E2AXXXSP, M37703E2BXXXSP
PROM Version of M37703M2-XXXSP, M37703M2AXXXSP, M37703M28XXXSp .... ·3-28 M37703E4-XXXSP, M37703E4AXXXSP, M37703E4BXXXSP
PROM Version of M37703M4-XXXSP, M37703M4AXXXSP, M37703M48XXXSp .... ·3-51
D APPENDICES
MELPS 7700 Mask ROM Ordering Method .. · .. · .. · .. · .. · ... · ... · ... · ... · .... -4-3 MELPS 7700 PROM Ordering Method ... , ... · .. · .... · .. · .. · .... · .. · ... 4-16 Mark Specification Form··· .. ·· .. ··· .. ·· .. · .. ··· .. ··· .. ··· .. ··· .. ··· ... ··· '4-29 Contact Addresses for Further Information
GUIDANCE
MITSUBISHI MICROCOMPUTERS
INDEX BY FUNCTION
.MELPS 7700 16-BIT MICROCOMPUTERS
Type
M37702M2-XXXFP
M37702M2AXXXFP
M37702M2BXXXFP
M37702S1FP
M37702S1AFP
M37702S 1 BFP
M37702M4-XXX FP
M37702M4AXXXFP
M37702M4BXXXFP
M37702S4FP
M37702S4AFP
M37702S4BFP
M37703M2-XXXSP
M37703M2AXXXSP
M37703M2BXXXSP
M37703S1SP
M37703S1ASP
M37703S1 BSP
M37703M4-XXXSP
M37703M4AXXXSP
M37703M4BXXXSP
M37703S4SP
Circuit function and organization StructurE
16K-Byte Mask-Prog. ROM, 512-Byte RAM
16-Bit Timer, 8-Bit A-D Converter C, Si Two Serial I/O
16K-Byte Mask-Prog. ROM, 512-Byte RAM
16-Bit Timer, 8-Bit A-D Converter C, Si Two Serial I/O
16K-Byte Mask-Prog. ROM, 512-Byte RAM
16-Bit Timer, 8-Bit A-D Converter C, Si Two Serial I/O
External ROM, 512-Byte RAM
16-Bit Timer, 8-Bit A-D Converter C, Si Two Serial I/O
External ROM, 512-Byte RAM
16-Bit Timer, 8-Bit A-D Converter C, Si Two Serial I/O
External ROM, 512-Byte RAM
16-Bit Timer, B-Bit A-D Converter C, Si Two Serial I/O
32K-Byte Mask-Prog. ROM, 2048-Byte RAM
16-Bit Timer, 8-Bit A-D Converter C, Si Two Serial I/O
32K-Byte Mask-Prog. ROM, 204B-Byte RAM
16-Bit Timer, 8-Bit A-D Converter C, Si Two Serial I/O
32K-Byte Mask-Prog. ROM, 2048-Byte RAM
16-Bit Timer, 8-Bit A-D Converter C, Si Two Serial I/O
External ROM, 2048-Byte RAM
16-Bit Timer, 8-Bit A-D Converter C, Si Two Serial I/O
External ROM, 2048-Byte RAM
16-Bit Timer, 8-Bit A-D Converter C, Si Two Serial I/O
External ROM, 2048-Byte RAM
16-Bit Timer, 8-Bit A-D Converter C, Si Two Serial I/O
16K-Byte Mask-Prog. ROM, 512-Byte RAM
16-Bit Timer, 8-Bit A-D Converter C, Si Two Serial I/O
16K-Byte Mask-Prog. ROM, 512-Byte RAM
16-Bit Timer, 8-Bit A-D Converter C, Si Two Serial I/O
16K-Byte Mask-Prog. ROM, 512-Byte RAM
16-Bit Timer, 8-Bit A-D Converter C, Si Two Serial I/O
External ROM, 512-Byte RAM
16-Bit Timer, 8-Bit A-D Converter C, Si Two Serial I/O
External ROM, 512-Byte RAM
16-Bit Timer, 8-Bit A-D Converter C, Si Two Serial I/O
External ROM, 512-Byte RAM
16-Bit Timer, 8-Bit A-D Converter C, Si Two Serial I/O
32K-Byte Mask-Prog. ROM, 2048-Byte RAM
16-Bit Timer, 8-Bit A-D Converter C, Si
Two Serial I/O
32K-Byte Mask-Prog. ROM, 2048-Byte RAM
16-Bit Timer, 8-Bit A-D Converter C, Si Two Serial I/O
32K-Byte Mask-Prog. ROM, 2048-Byte RAM
16-Bit Timer, 8-Bit A-D Converter C, Si Two Serial I/O
External ROM, 2048-Byte RAM
16-Bit Timer, 8-Bit A-D Converter C, Si Two Serial I/O
. • MlTSUBlSHI . . . . ELECTRIC
Supply voltage (V)
5±10%
5±10%
5±10%
5±10%
5±1O%
5±10%
5±10%
5±10%
5±10%
5±10%
5±10%
5±10%
5±10%
5±10%
5±1O%
5±10%
5±10%
5±10%
5±10%
5±10%
5±10%
5±10%
Electrical characteristics Typ. Min. Max.
power cycle fre- Package Page dissipali time quency
(mW) (ns) (MHz)
30 500 8 80P6N
60 250 16 BOP6N
95 160 25 BOP6N
2-3
30 500 8 BOP6N
60 250 16 BOP6N
95 160 25 BOP6N
30 500 8 BOP6N
60 250 16 BOP6N
95 160 25 BOP6N
2-62
30 500 8 BOP6N
60 250 16 BOP6N
95 160 25 BOP6N
30 500 8 64P4B
60 250 16 64P4B
95 160 25 64P4B
2-65
30 500 B 64P4B
60 250 16 64P4B
95 160 25 64P4B
30 500 8 64P4B
60 250 16 64P4B
2-84
95 160 25 64P4B
30 500 8 64P4B
1-3
.MELPS 7700 16-BIT MICROCOMPUTERS (Continue)
Type
M37703S4ASP
M37703S4BSP
M37720S1FP
M37720S1AFP M37730S2FP M37730S2AFP M37730S28FP M37730S2SP M37730S2ASP M37730S28SP M37732S4FP
M37732S4AFP
M37732S48FP
1-4
Circuit function.and organization Structute
External ROM, 2048-Byte RAM
16-Bit Timer, 8-Bit A-O Converter C, Si Two Serial 1/0
External ROM, 2048-Byte RAM
16-Bil Timer, 8-Bit A-O Converter C, Si Two Serial 1/0
Exlemal ROM, 512"Byte RAM
16-Bit Timer, 8-Bil A-O Converter C, SJ Two Serial 1/0, OMAlORAM Controller
External ROM, 512-Byte RAM
16-Bit Timer, 8-Bil A-O Converter C,Si
Two SerJal 1/0, OMAlORAM Controller
External ROM, 1024-Byte RAM C,Si
16-Bit Timer, Serial 1/0
External ROM, 1024-Byte RAM C,Si
16-Bit Timer, Serial 1/0
External ROM, 1024-Byle RAM C,Si
16-Bit Timer, Serial 1/0
External ROM, 1024-Byte RAM C, Si
16-Bit Timer, Serial 1/0
External ROM, 1024-Byle RAM C, Si
16-Bit Timer, Serial 110
External ROM, 1024-Byte RAM C, Si
16-Bil Timer, Serial 1/0 External ROM, 2048-Byte RAM
16-Bit Timer, 8-Bit A-O Converter C, Si Two Serial 1/0
External ROM, 2048-Byte RAM
16-Bit Timer, 8-Bit A-O Converter C, Si Two Serial 1/0
External ROM, 2048-Byte RAM
16-Bit Timer, 8-Bit A-O Converter C, Si Two Serial 1/0
.•... ... MITSlBSH. I . . . . ELECTRIC
MITSUBISHI MICROCOMPUTERS
INDEX BY FUNCTION
Eleclncal characteristics Supply TYP· Min. Max.
voltage ppwer cycle Ire- Package Pag~
(V) dissipatiar time quency (mW) (ns) (MHz)
5±10% 60 250 16 64P48
2'-'84
5±10% 95 160 25 64P48
5±10% 30 500 8 HioP6S
2--:-86
5±10% 60 250 16 100P6S
5±10% 30 500 8 64P6N
5±10% 60 250 16 64P6N
5±10% 95 160 25 64P6N
2--,179
5±10% 30 500 8 64P48
5±10% 60 250 16 64P48
5±10% 95 160 25 64P48
5±10% 30 500 8 80P6N
5±10% 60 250 16 80P6N 2-237
5±10% 95 160 25 80P6N
MITSUBISHI MICROCOMPUTERS
INDEX BY FUNCTION
.PROGRAMMABLE ROM MICROCOMPUTERS
Electrical characteristics Supply Typ. Min. Max.
Type Circuit function and organization Structure voltage power cycle fre- Package Page (V) dissipalion time quency
(mW) (ns) (MHz) M37702E2-XXXFP One time PROM Version of M37702M2-XXXFP
C, Si 5±10% 30 500 8 80P6N
16K-Byte PROM, 512-Byte RAM
M37702E2AXXXFP One time PROM Version of M37702M2AXXXFP
C, Si 5±10% 60 250 16 80P6N 16K-Byte PROM, 512-Byte RAM
M37702E2BXXXFP One time PROM Version of M37702M2BXXXFP
C, Si 5±10% 95 160 25 80P6N 16K-Byte PROM, 512-Byte RAM
EPROM Version of M37702M2-XXXFP 3-3
M37702E2FS
16K-Byte EPROM, 512-Byte RAM C, Si 5±1O% 30 500 8 8000
M37702E2AFS EPROM Version of M37702M2AXXXFP
C, Si 5±10% 60 250 16 8000
16K-Byte EPROM, 512-Byte RAM M37702E2BFS EPROM Version of M37702M2BXXXFP
C, Si 5±10% 95 160
I
25 800016K-Byte EPROM, 512-Byte RAM
M37702E4-XXX FP One time PROM Version of M37702M4-XXXFP
C, Si 5±10% 30 500 8 80P6N
32K-Byte PROM, 2048-Byte RAM
M37702E4AXXX FP One time PROM Version of M37702M4AXXXFP
C, Si 5±1O% 60 250 16 80P6N 32K-Byte PROM, 2048-Byte RAM
M37702E4BXXXFP One time PROM Version of M37702M4BXXXFP
C, Si 5±10% 95 160 25 80P6N 32K-Byte PROM, 2048-Byte RAM
3-26 M37702E4FS EPROM Version of M37702M4-XXXFP
C, Si 5±1O% 30 500 8 8000
32K-Byte EPROM, 2048-Byte RAM M37702E4AFS EPROM Version of M37702M4AXXXFP
C, Si 5±10% 60 250 16 8000
32K-Byte EPROM, 2048-Byte RAM M37702E4BFS EPROM Version of M37702M4BXXXFP
C, Si 5±10% 95 160 25 8000
32K-Byte EPROM, 2048-Byte RAM
M37703E2-XXXSP One time PROM Version of M37703M2-XXXSP
C, Si 5±10% 30 500 8 64P4B
16K-Byte PROM, 512-Byte RAM
M37703E.2AXXXSP One time PROM Version of M37703M2AXXXSP
C, Si 5±10% 60 250 16 64P4B 3-28
16K-Byte PROM, 512-Byte RAM
M37703E2BXXXSP One time PROM Version of M37703M2BXXXSP
C, Si 5±10% 95 160 25 64P4B 16K-Byte PROM, 512-Byte RAM
M37703E4-XXXSP One time PROM Version of M37703M4-XXXSP
C, Si 5±10% 30 500 8 64P4B
32K-Byte PROM, 2048-Byte RAM
M37703E4AXXXSP One time PROM Version of M37703M4AXXXSP
C, Si 5±10% 60 250 16 64P4B 3-51
32K-Byte PROM, 2048-Byte RAM
M37703E4BXXXSP One time PROM Version of M37703M4BXXXSP
C, Si 5±10% 95 160 25 64P4B 32K-Byte PROM, 2048-Byte RAM
1-5
MITSUBISHI MICROCOMPUTERS
DEVELOPMENT SUPPORT SYSTEMS
Development support systems for MELPS 7700
MELPS 7700
Assembler Emulation pod For evaluate
type name M37702M2-XXXFP M37702M2AXXXFP M37702S1FP M37702S1AFP
M37702T-HPO M37702E2-XXXFP
M37702E2AXXXFP M37702E2FS M37702E2AFS M37702M4-XXXFP
M37702M4AXXXFP M37702E2FS
M37702S4FP M37702E2AFS
M37702S4AFP M37702T -HPO M37702E2BFS
M37702E4-XXXFP (Exchange MCU for M37702S4AFP) M37702E4FS
M37702E4AXXXFP M37702E4AFS
M37702E4FS M37702E4BFS
M37702E4AFS M37702M2BXXXFP M37702S1 BFP
M37702TB-HPO**
M37702E2BXXXFP M37702E2BFS M37702M4BXXXFP
M37702S4BFP M37702TB-HPO**
M37702E4BXXXFP (Exchange MCU for M37702S4BFP)
M37702E4BFS M37703M2-XXXSP
M37703M2AXXXSP RASM77
M37703S1SP
M37702T-HPO M37703S1 ASP
M37703E2-XXXSP
I
M37703E2AXXXSP
M37703M4-XXXSP M37703E2-XXXSP
M37703M4AXXXSP M37703E2AXXXSP
M37703S4SP M37702T-HPO M37703E2BXXXSP
M37703S4ASP (Exchange MCU for M37702S4AFP) M37703E4-XXXSP
M37703E4-XXXSP M37703E4AXXXSP
M37703E4AXXXSP M37703E4BXXXSP
M37703M2BXXXSP
M37703S1 BSP M37702TB-HPO**
M37703E2BXXXSP M37703M4BXXXSP
M37702TB-HPO**
M37703S4BSP
(Exchange MCU for M37702S4BFP) M37703E4BXXXSP
M37720S1FP
M37720T -H PO** -
M37720S1AFP M37730S2FP M37730S2AFP
M37730T-HPO**
M37730S2SP M37730S2ASP
-
M37730S2BFP
M37730TB-HPO**
M37730S2BSP M37732S4FP
M37732T-HPO**
M37732S4AFP -
M37732S4BFP M37732TB-HPO**
**
Under development1-6
MITSUBISHI MICROCOMPUTERS
DEVELOPMENT SUPPORT SYSTEMS
Program writing adapter for built-in PROM type microcomputers of MELPS 7700 Built-in PROM type
microcomputers type name M37702E2-XXXFP
M37702E2AXXXFP M37702E2BXXXFP M37702E2FS M37702E2AFS M37702E2BFS M37702E4-XXXFP M37702E4AXXXFP M37702E4BXXXFP M37702E4FS M37702E4AFS M37702E4BFS M37703E2-XXXSP M37703E2AXXXSP M37703E2BXXXSP M37703E4-XXXSP M37703E4AXXXSP M37703E4BXXXSP
Program writing adapter
PCA4774
PCA4708
PCA4774
PCA4708
PCA4709
• MITSUBISHI
... ELECTRIC
1-7MITSUBISHI MICROCOMPUTERS
ORDERING INFORMATION
FUNCTION CODE
Mitsubishi integrated circuit may be ordered using the following simplified' alphanumeric type-codes which define the func- tion of the IC/lSls and the package style.
For Mitsubishi
Example:
M 3
T
Original Products
77 02 E 4 001 FP
-, T
~ - - , - M : Mitsubishi integrated prefix3 : Represent an original singlecchip microcomputer Series designation using 2 digits
Circuit function identification code using 2 digits Memory identification code using a digit
[
E : PROM P : Piggyback
M : Mask ROM 5 : External ROM N : Mask ROM+EEPROM
Memory size identification code using a digit Normally, using hyphen.
J
When electrical characteristic, or division of quality identification code using alphanumeric character.
T : For automobile, industrial equipment Mask ROM number
Package style
[ .
J : PlCC, or SOJ package FP : Molded plastic flat package F5 : Ceramic flat package 5P : Molded plastic shrink package 55 : Ceramic shrink package
PACKAGE CODE
Package style may be specified by using the following simplified alphanumeric code.
1-8
Example:
64 P 4 B
' - - - j - - + - - j - -Number of pins ' - - j - . - - t -Package structure
[
K: Glass-sealed ceramic ] P : Molded plastic
5 : Metal-sealed ceramic Package outline
[
0 : PlCC, SOJ 1 : DIP 2 : SOP
Secondary outline code
4 : DIP
l
6 :QFP
J
Special-purpose secondary codes describing outline are' included as necessary. For details, contact your sales representative.
• MITSUBISHI
. . . . ELECTRIC
MITSUBISHI MICROCOMPUTERS
PACKAGE OUTLINES
64P4B Plastic 64pin 750mil SDIP
eJl
1. 778 TO. 25
56 4 +0.5 . -0.2
64P6N Plastic 64pin QFP
"'Nt
0 0
00 +1
'"
a
® ®
®
®
·31
O.6±O.2
., MITSUBISH
~ELECTRIC'
Dimension in mm
_ _ _ 19_--=:2~
Dimension in mm
1-9
MITSUBISHI MICROCOMPUTERS
PACKAGE OUTLINES
8000 Ceramic 80pin LCC
Dimension in mm 21.0±0.2
<1>68.8
18. 40±0. 15
aOP6N Plastic 80pin QFP
Dimension in .mmIQl) @)
!f= ~t
o ®I @CD @ x « :::;:
~ 0-;
UUL [lUll[
.6±0.2
.l
14+0.2J ~ -
,o
.~ .llill nO[ Dl 1'\\ '
I
20±0.20.6±0.2
f*
22.8+0.3
I
16.8+0.3 d1-10
100P6S Plastic 100pin QFP
~~~fn-uruuuuu.~-=~j ci I.
20±O.2 O.6±O.2• 22.8
MITSUBISHI MICROCOMPUTERS
PACKAGE OUTLINES
Dimension in mm
k - - - ' 2 . : = ' - - - . . I 6 +1
16.8
1-11
MITSUBISHI MICROCQMPUTERS
LETTER SYMBOLS FOR· THE··DYNAMIC ·PARAMETERS"
"1. INTRODUCTION
A system 'of letter symbols to be used to represent the dynamic parameters of intergrated circuit memories and other 'sequential circuits especially fQr single-chip micro- computers, microprocessors and LSls for peripheral circuits has been discussed internationally in the TC47 of the International Electrotechnical Committee (lEC).
Finally the IEC has decided on the meeting of TC47 in February 1980 that this system of letter symbols will be a Central Office document and circulated to all countries to vote which means this system of letter symbols will be a international standard.
The system is applied in this LSI data book for the new products only. Future editions of this data book will be applied this system. The IEC document which describes "Letter symbols for dynamic parameters of sequential integrated circuits, including memories" is introduced below. In this data book, the dynamic para- meters in the IEC document are applied to timing reCluirements and switching characteristics.
2 .. LETTER SYMBOLS
The system of letter symbols outlined in this document enables symbols to be generated for the dynamic para- meters of complex sequential circuits, including memo- ries, and also allows these symbols to be abbreviated to simple mnemonic symbols when no ambiguity is likely to arise.
2.1. General Form
The dynamic parameters are represented by the general symbol of the form:-
tA(BC-DC)F ... (1) where:
Subscript A indicates the type of dynamic parameter being represented, for example; cycle time, setup time, enable time; etc.
Subscript B indicates the name of the signal or terminal for which a change of state or level (or establishment of a state or level) con- stilutes a signal event assumed to occur first, that is, at the beginning of the time interval. If this event actually occurs last, that is, at the end of the time interval, the value of the time interval is negative.
Subscript C indicates .the direction of the transition and/or the final state or level of the signal represented by B. When two letters are used, the initial state or level is also indi- cated.
1-12
Subscript 0 indicates the name of the signal or terminal for which a change of state or level (or establishment of a state or, ,level) consti- tutes a signal· event ass'u'med to occur, last, that is, at the end of the time interval. If this event actually occurs first, that is, at the beginning of the time interval, the value of the time interval is negative.
Subscript E indicates the direction of the transition and/or the final state or level of the signal represented by D. When two letters are used, the initial state or level is also indi- ca.ted.
Subscript F indicates additional information such as mode of operation, test conditions, etc.
Note 1: Subscripts A to F may each consists of one or more letters.
2" Subscripts 0 and E are not used for transition times.
3: The "-" in the symbol (1) above is used to indicate "to"; hence the sym- bol represents the time interval from signal event B occuring to signal event 0 occuring. and it is important to note ,that this convention is used for all ',dynamic parameters including hold times. Where no misunder- standing can occur the hyphen may be omitted.
2.2. Abbreviated Form
The general symbol given above may be abbreviated whim no misunderstanding is lil<ely to arise. For example to:
or tA(B)
or tA(D) often used for hold times or tAF no brackets are used in th is case or tA
or tBe-DE often used for unclassified time intervals
2.3. Allocation of Subscripts
In allocating letter symbols for the subscripts, the most commonly used subscripts are given single letters where practicable and those less commonly used are designated by up to three letters. As far as possible, some form of mnemonic representation is used. Longer letter symbols maybe, used for specialised signals or terminals if this aids understanding.
3. SUBSCRIPT A
(For Type of Dynamic Parameter)
The subscript A represents the type of dynamic para- meter to be designated by the symbol and', for memo- ries, the parameters may be divided into two classes:a) those that are timing requirements for the memory and
MITSUBISHI MICROCOMPUTERS
LETTER SYMBOLS FOR THE DYNAMIC PARAMETERS
b) those that are characteristics of the memory.
The letter symbols so far proposed for memory circuits are listed in sub·clauses 3.1 and 3.2 below.
All subscripts A should be in lower-case.
3.1. Timing Requirements
The letter symbols for the timing requirements of semi- conductor memories are as follows·:
Term Cycle time
Time interval between two signal events Fall time
Hold time Precharging time Rise time Recovery time Refresh time interval Setup time
Transition time Pulse duration (width)
3.2. Characteristics
Subscript c d f h pc rec rf su w
The letter symbols for the dymmic characteristics of semiconductor memories are as follows:
Characteristic Subscript
Access time a
Disable time dis
Enable time en
Propagation time p
Recovery time rec
Transition time T
Valid time v
Note: Recovery time for use as a characteristic is limited to sense recovery time
4. SUBSCRIPTS BAND D
(For Signal Name or Terminal Name)
The letter symbols for the signal name or the name of the terminal are as given below.
All subscripts Band D should be in upper-case.
Signal or terminal Subscript
Address A
Clock C
Column address CA
Column address strobe CAS
Data input D
Data input/output DO
Chip enable E
Erasure ER
Output enable G
Program PR
Data output 0
Read R
Row address RA
Row address strobe RAS
Refresh RF
Read/Write RW
Chip select S
Write (write enable) W
Note 1 In the letter symbols for time intervals. bars over the subscripts. for ex ample CAS, should not be used
2 It should be noted, when further letter symbols are chosen, that the sub·
script should not end with H, K, V. X, or Z, (See clause 5)
3 If the same terminal, or signal, can be used for two functions {for example Data Input/output, ReadNVritel the waveform should be labelled With the dual function, if appropriate, but the symbols for the dynamic parameters should include only that part of the subscript relevant to the parameter
5. SUBSCRIPTS C AND E (For Transition of Signal)
The following symbols are used to represent the level or state of a signal:
Transition of signal High logic level
Low logic level
Subscript H L Valid steady-state level (either low or high) V Unknown, changing, or 'don't care' level X High-impedance state of three·state output Z The direction of transition is expressed by two letters, the direction being from the state represented by the first letter to that represented by the second letter, with the letters being as given above.
When no misunderstanding can occur, the first letter may be omitted to give an abbreviated symbol for sub- scripts C and E as indicated below.
All subscripts C and E should be in upper-case.
Subscript
Examples Full Abbreviated
Transition from high level to
low level HL L
Transition from low level to
high level LH H
Transition from unknown or
changi ng state to val id state XV V Transition from valid state to
unknown or changing state VX X
Transition from high-impedance
state to valid state ZV V
Note Since subscripts C and E may be abbreviated, and since subscripts Band D may contain an indeterminate number of letters, it is necessary to put.the restriction on the subscripts Band 0 that they should not end with H, L, V, X, or Z, so as to avoid possible confusion
• MITSUBISHI
. . . . ELECTRIC
1-13MITSUBISHI MICROCOMPUTERS
LETTER SYMBOLS FOR THE DYNAMIC PARAMETERS
6. SUBSCRIPT F (For Additional Information)
If necessary, subscript F is used to represent any addi- tional qualification of the parameter such as mode of operation, test conditions, etc_ The letter symbols for subscript F are given below_
Subscript P sh.ould be in upper-case_
Modes of operation Power-down
Page-mode read Page-mode write Read
Refresh
Read-modify-write Read-write Write
1-14
Subscript PO PGR PGW R RF RMW RW W
'.. . MITSUBISHI
. . . . ELECTRIC
MITSUBISHI MICROCOMPUTERS
SYMBOLOGY
FOR DIGITAL INTEGRATED CIRCUITS
New symbol. Former symbol Parameter-definition
C, Input capacitance
Co Output capacitance
C,o Input/output tanninal capacitance
C'(~I Input capacitance of clock input
I Frequency
I(~I Clock frequency
I Current-the current into an integrated circuit terminal is defined as a positive value and the current out of a terminal is defined as a negative value
IBB Supply current from Vee
IBB(AV) Average supply current from Vae
lee Supply current from Vee
ICC(AV) Average supply current from Vee
Icc{po) Power-down supply current from Vee
100 Supply current from Voo
IOO(AV) Average supply current from Voo
laa Supply current from VaG
IGG(AV) Average supply current from VGG
I, Input current
I'H High-level input current-the value of the input current when VOH is applied to the input considered I'L Low-level input current-the value of the input current when VOL is applied to the input considered 10H High-level output current-the value at the output current when VOH is applied to the output considered 10L Low-level output current-the value of the output current when VOL is applied to the output considered
loz Otf-state(high-impedance state)output currerit-Itle current Into an output having a three-state capability with input condition so applied that it will establish according to the product specification, the off(high-impedance)state at the output
IOZH Otf-state(high-impedance state) output current, with high-level voltage applied to the output IOZL Otf-state(high-impedance state) output current, with low-level voltage applied to the output
los Short-circuit output current
Iss Supply current from Vss
Pd Power dissipation
NEW Number of erase/write cycles
NRA Number of read access unrefreshed
R, Input resistance
RL External load resistance
ROFF Off-state output resistance
RON On-state output resistance
la Access time-the time interval between the application of a specified input pulse during a read cycle and the availability of valid data signal at an output la(AI la(ADI Address access time-the tJme interval between the application of an address input pulse and the availability of valid data'signals at an output
ta{cAs) Column address strobe access time
la(EI la(eEI Chip enable access time la(al la(oEI Output enable access time
ta(PR) Data access time after program
la(RASI Row address strobe access time la(sl la(esl Chip select access time
Ie Cycle time
IeR Ie(RDI Read cycle time-the time interval between the start of a read cylce and the start of the next cycle
tCRF le(REFI Refresh cycle time-the time Interval between successive signals that are intended to restore the level in a dynamic memory cell to its original level
t CPG le(pal Page-mode cycle time
tCRMW tC{RMW) Read-modify-write cycle time-the time interval between the start of a cycle in which the memory is read and new data is entered, and the start of the next cycle
lew tC(WR) Write- cycle time-the time interval between the start of a write cycle ,and the start of the next cycle
1-15
New symbol Former symbol
td(CAS~RAS)
td(CAS-W) td(RAS-CAS) td(RAS-W) tdiS(R-O) tdis(s) tdis(w) tOHL tOLH len(A-O) teneR-oj tents-oj tf th theA) theA-E) theA-PRJ th(CAS-CA) th(CAS-D) th(CAS_Q)
th(CAS-RAS) th(cAs-w) th(D) th(D-PR) theE) theE-D) theE-G) th(R) th(RAS-CA)
the RAS-CAS) th(RAS-O) th(RAS-W) th(s) thew) th(W-CAS) th(W-D) thew-RAS) tpHt.:.
tpLH
tr
trec(w) trec(po) tsu
tSU(A) ISU(A-E) tSU(A-W) tSU(CA-RAS)
1...,16
td(RAS-WR) tdis(R-DA) tp~z(CS) tPXZ(WR)
tpzv(A-OQl tPZV(R-OQ) tpzx( cs-co)
thlAD) th(AD-CE) th{AD-PRO)
th(CAS-DA) th(CAS-OUT)
th(CAS-WR) th(DA) theDA-PRO) thlCE) th(CE-DA) th(CE-OE) th(RD)
th(RAS-DA) th(RAS-WR) th(cs) th(WR) th(WR-CAS) th(WR-DA) th(WR-RAS)
twr
tSU(AO) tSU(AD-CE) tSU(AD-WR)
MITSUBISHI MICROCOMPUTERS
Parameter-definition
Delay time-the time between the specified reference pOints on two pulses
Delay time between clock pulses-a:g., symbology,. delay time, .clock 1 to clock 2 or clock 2 to clock 1 Delay time, column address strobe to row address strobe
Delay time, column address strobe to write Delay time, row address strobe to column address strobe Delay tim.e, row address strobe to write
Output disable time after read Output disable time after chip select.
Output disable time after write
SYMBOLOGY
High-level to low-level delay ti.me ) the time interval between specified reference points on the input and on the output pulses when the output is Low-level to high-level delay time going to the low (high)level and when the device is driven with a specified loading networks
Output enable time after address Output enable time after read Output enable time after chip select Fall time
Hold time-the interval 01 time during which a signal at a specified input terminal appears after an active transition occurs at another specified input tenninal Address hold time
Chip enable hold time after address Program hold time after address
Column address hold time after column address strobe Data-in hold time after column address strobe Data-out hOld time after column address strobe Row address strobe hold time after column address strobe Write hold time after column address strobe Data-in hold time
Program hold time after data-in Chip enable hold time Data-in hold time after chip enable Output enable hold ti~e after chip enable·
Read hold time
Column address hold time after row address strobe Column address strobe hold time after row address strobe Data-in hold time after rOw address strobe
Write hold time after row address strobe Chip select hold time
Write hold time
Column .address strobe hold time after write Data-in hold time after write
Row address ·hold time after write High-level to low-level propagation time ) Low-level to high-level propagation time Rise time
the time interval between specified reference points on the input and on the output pulses when the output is going to the low (high)level and when the device is driven and loaded by typical devices of state~ type
Write recovery time-the time interval between the termination of a write pulse and the initiation of a new cycle Power-down recovery time
. Setup time-the time interval between the application of a Signal ~hiCh is maintained at a speciifed input, terminal a!:ld a cOflsecutive active tarnsltion at another specified input terminal
Address setup time
Chip enable setup time before address Write setup time before address
Row address strobe setup time belore column addr'ess.
New symbol Former symbol
t5U (D) tSU(DA)
tSU(D-E} tSU(DA-GEl
tsu(o-w) tSU(DA-WR) tSU(E) tsuCCE )
tSU(E-P) tsuCCE-p)
tSU(G-E) tSU(OE-GEl
tSU(P-E} tSU(P-CE}
tSU(PD)
tSUCR) tSU(RD)
tSUCR-CAS) tSU(RA-CAS) tSU(RA-CAS)
tsu(s) tsu(cs}
tSU(S-w) tSU(CS-WR)
tsu(w) tSU(WR)
hHL tTlH
tV(AJ tdV(AOJ
tV(EJ tdv(eEi
tV(EJPR tvCCEJPR
tV(G) tV(OE)
tV(PR)
tv(s) tv(cs)
tw
tW(E) tW(CE)
tWCEH) tW(CEH)
tW(ELJ tW(ELJ
tW(PRJ
tW(R) tW(RD)
tw(S) twCCs)
tw(w) tWCWR)
tw(.p) Ta Topr Tstg VBB
Vee VDD
VGG V, V'H V'L Vo V OH VOL Vss
MITSUBISHI MICROCOMPUTERS
SYMBOLOGY
Parameter-definition Data-in setup time
Chip enable setup time before data-in Write setup time before data-in Chip enable setup time
Precharge setup time before chip enable Chip enable setup time before output enable Chip enable setup time before precharge Power-down setup time
Read setup time
Column address strobe setup time before read Cloumn address strobe setup time before row address Chip select setup time
Write setup time before chip select Write setup time
High-level to low-level transition time
I
the time interval between specified reference points on the edge of the output pulse when the output is going to the 10w(high)level and when a specified input signal is applied through a specified network and Low-level to high-level transition time the output is loaded by another specified networkData valid time after address Data valid time after chip enable
Data valid time after chip enable in program mode Data valid time after output enable
Data valid time after program Data valid time after chip select
Pulse width (pulse duration)the time interval between specified reference points on the leading and training edges of the waveforms Chip enable pulse width
Chip enable high pulse width Chip enable low pulse width Program pulse wiqth Read pulse width Chip select pulse width Write pulse width Clock pulse width Ambient temperature Operating temperature Storage temperature VBB supply voltage Vee supply voltage Voo supply voltage VGG supply voltage Input voltage
High-level input voltage-the value of the permitted high-state voltage at the input Low-level input voltage--=-the value of the permitted low-state voltage at the input Output voltage
High-level output voltage-the value of the guaranteed high-state voltage range at the output Low-level output voltage,.-the value of the guaranteed low-state voltage range at the output
V ss supply voltage
• MITSUBISHI
"'ELECTRIC
1-17MITSUBISHI MICROCOMPUTERS
···QUALITY ASSURANCE AND RELIABILITY TESTING
1 INTRODUCTION
IC & LSI have made rapid technical progress in electrical performances of high integration, high speed, and sophisti- cated functionality. And now they have got boundless wider applications in electronic systems and electrical ap- pliances.
To meet the above trend of expanding utilization of IC &
LSI, Mitsubishi considers that it is extremely important to supply stable quality and high reliable products to cus- tomers.
Mitsubishi Electric places great emphasis on quality as a basic policy "Quality First", and has striven always to im- prove quality and reliability.
Mitsubishi has already developed the Quality Assurance System covering design, manufacturing, inventory and de- livery for IC & LSI, and has supplied highly reliable pro- ducts to customers for many years. The following articles describe the Quality Assurance System and examples of reliability control for Mitsubishi Single-chip 16-bit Micro- computer.
2. QUALITY ASSURANCE SYSTEM
The Quality Assurance System places emphasis on built-in reliability in designing and built-in quality in manufacturing.
The System from development to delivery is summarized in Figure 1.
2.1 Quality Assurance in Designing
The following steps are applied in the designing stage for a new product.
(1) Setting of perfomance, quality and reliability target for new product.
(2) Discussion of performance and quality for circuit de"
sign, device structure, process, material and package.
(3) Verification of design by CAD system to meet standar- dized design rule:
(4) Functional evaluation for bread-board device to confirm electrical performance.
(5) Reliability evaluation for TEG (Test Element Group) chip to detect !>asic failure mode and investigate fai- lure mechanism.
(6) Reliability test (In-house qualification) for new product to confirm quality and reliability target.
(7) Decision of pre-production from the standpoint of per- formance, reliability, production flow/conditions, pro- duction capability, delivery etc.
2.2 Quality Assurance in Manufacturing
Quality assurance in manufacturing is performed as follows.
(1) Environment control such as temperature, humidity and dust as well as deionized water and utility gases.
(2) Maintenance and calibration control for automatized manufacturing equipments, automatic testing equip- ments, and measuring instruments.
1-18
(3) Material control such as silicon wafer, lead frame, packaging material, mask and chemicals.
(4) In-process inspections in wafer-fabrication, assembly and testing.
(5) 100% final inspection of electrical characteristics, visual inspection and burn-in, ii necessary.
(6) Quality assurance test
-Electrical characteristics and visual inspection, lot by lot sampling
-Environment and endurance test, periodical sampling.
(7) Inventory and shipping control, such as storage en- vironment, date code identification, handling and ESD (Electro Static Discharge) preventive procedure.
2.3 Reliability Test
To verify the reliability of a product as described in the Mit- subishi Quality Assurance System, reliability tests are per- formed at three different stages in new product develop- ment, pre-production and mass-production.
At the development of a new product the reliabi.lity test plan is fixed corresponding to the quality and reliability target of each product, respectively. The test plan includes in-house qualification test and TEG evaluation, if necessary.
TEG chips are designed and prepared for new device structure, new process and new material.
After the proto-type product has passed the in-house qual- ification test, the product advances to the pre-production. In the pre-production stage, the specific reliability tests are programmed and performed again to verify the quality of pre-production product.
In the mass production, the reliability tests are performed periodically to confirm the quality of the mass production product according to the quality assurance test program.
Table 1 shows an example of reliability test program for plastiC encapsulated IC & LSI.
Table 1 TYPICAL RELIABILITY TEST PROGRAM FOR PLASTIC ENCAPSULATED IC & LSI
Group Test Test condition
1 Solderability 230'C, 5sec. Rosin flux Soldering heat 260'C, lOsec.
2 Thermal shock -55'C, 125'C, 15cycles Temperature cycling -65'C, 150'C, 100cycles
3 Lead fatigue 250gr, 90', 2arcs
Shock 1500G, O. 5msec.
20G, 100-2000Hz
4 Vibration X, Y,.Z direction
4min.lcycle, 4cycles/direction Constant acceleration 20000G, Y direction, 1 min.
5 Operation life T a= 125'C, Vccmax
1000hours 6 High temperature
T a= 150'C, 1000hours storage life
High temperature and
85'C ,85%, 1000hours 7 high humidity
Pressure cooker 121'C, 100%, 100hours
MITSUBISHI MICROCOMPUTERS
QUALITY ASSURANCE AND RELIABILITY TESTING
DESIGNI QUALITY
STAGE MARKET SALES PRODUCTION MANUFACTURING ASSURANCE
ENGINEERING
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• MlTSUBlSHI
"ELECTRIC
PRODUCTION CONTROL
)
u:;
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1-19
I
MITSUBISHI MICROCOMPUTERS
QUALITY ASSURANCE AND RELIABILITY TESTING
2.4 Returned Product Control
When failure analysis is requested by a customer, the failed devices are returned to MitsubishiElectric via the sales office of Mitsubishi using the form of "Analysis Re- quest of Returned Product"
Mitsubishi provides various failure analysis equipments to analyze the returned product. A failure analysis report is
FAILURE ANALYSIS
generated to the customer upon completion of the analysis.
The failure analysis result enforces taking corrective action for the design, fabrication, assembly or testing of the pro- duct to improve reliability and realize lower failure rate.
Figure 2 shows the procedure of returned product control from customer.
r - - - ,
CLASSIFICATION OF FAILURE MODES ACCEPTANCE
is
;::
() L1J
...,
...---;--I~
INTERNAL VISUAL INSPECTION
CHIP ANALYSIS
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Fig;2 PROCEDURE OF RETURNED PRODUCT CONTROL
1-20
~M~I
SURVEY OF PROCESS RECORD
MITSUBISHI MICROCOMPUTERS
QUALITY ASSURANCE AND RELIABILlry TESTING
3 RELIABILITY TEST RESULTS
The reliability test results for Mitsubishi Single-chip l6-bit Microcomputers are shown in Table 2.
Table 2 shows the result of endurance tests of high temper-
ature operation life and high temperature storage. life test and the results of the environment tests of thermal stress, high temperature/high humidity and pressure cooker test for the single-chip l6-bit Microcomputer.
Table 2 ENDURANCE and ENVIRONMENTAL TEST RESULTS
Test . Series Type Number Test Condition Number of Device Hours Number of
Samples (Hours) Failures M37702M2BXXXFP
M37702M4BXXXFP M37703M4BXXXSP
High Temperature M37720S1 AFP
MELPS 7700 M37730S2BFP 125t 7V 198 200000 0
Operation Life
M37730S2BSP M37732S4BFP M37702E2AXXXFP M37703E4AXXXSP High Temperature
MELPS 7700 ditto 150°C 198 200000 0
Storage Life Low Temperature
MELPS 7700 M37702M2BXXXFP
-55t 44 88000 0
Storage Life M37702E4AXXXFP
M37702M2BXXXFP M37702M4BXXXFP M37703M4BXXXSP
High Temperature M37720S1AFP
85°C85%RH
MELPS 7700 M37730S2BFP 198 200000 0
High Humidity Life
M37730S2BSP 5.5V
M37732S4BFP M37702E2AXXXFP M37703E4AXXXSP
Test Series Type Number
I
Test Conditionr
Number ofT Number of Failures1
Samples f 96Hours
I
240HoursI
Pressure Cooker MELPS 7700 ditto
I
121tl00%RHI
198I
0I
0I
Test Series Type Number Test Condition Number of Number of Failures
Samples 10Cycles
I
100Cycles TemperatureMELPS 7700 ditto -65°C 30min
198 0
I
0Cycling 150t 30min
1-21
MITSUBISHI MICROCOMPUTERS
'QUALITY ASSURANCE AND RELIABILITY TESTING
4 FAILURE ANALYSIS
Accelerated reliability tests are applied to observe failures casued by temperature, . voltage, humidity, current, mecha- nical stress and those combined stresses on chips and packages.
Examples of typical failure modes are shown below.
{1) Wire Bonding Failure by Thermal Stress
Figure 3, Figure 4 and Figure 5 are examples of a fai- lure occured by high temperature storage test of 225°C, 1000hours.
Au-AI intermetallic formation, so-called "Purple plague" by thermal overstress makes Au wire lift off from aluminum metallization. The activation energy of this failure mode is estimated at approximately 1.0eV and no failure has been observed so far in practical uses.
Flg.3
Micrograph of lifted Au ball trace on AI bonding pad
Flg.4 Flg.S
Au-AI plague formation on bonding pad
Lifted Au wire ball base
(2) Aluminum Corrosion Failure by Temperature/Humidity Stress.
Figure 6, Figure ? and Figure 8 are examples of cor- roded failure of aluminum metallization of plastiC en- capsulated IC after accelerated temperature/humidity storage test (pressure cooker test) of 121°C, 100%RH, 1000hours duration.
Aluminum bonding pad is dissolved by penetrated wa- ter from plastic package, and chlorine concentration is observed on corroded aluminum bonding pad as shown in Figure 8.
1-22
• ·MITSUBISHI
"'ELECTRIC
Fig.6
Micrograph of corroded Aluminum metallization
Fig.? Enlarged micrograph of c<;lrroded Aluminum bonding pad
Fig.8 CI distribution on corroded Aluminum bonding pad
MITSUBISHI MICROCOMPUTERS
QUALITY ASSURANCE AND RELIABILITY.TESTING
(3) Destructive Failure by Electrical Overstress
Surge voltage marginal tests have been performed to reproduce the electrical overstress failure in field uses.
Figure 9 and Figure 10 are examples of failure observed by surge voltage test. The trace of destruc- tion is verified as the aluminum bridge by X-ray micro analysis.
Fig.9 Micrograph of surge
(4) Aluminum Electromigration
Figure 11 shows an open circuit of aluminum metalliza- tion in high current density region caused by acceler- ated operation life test. This failure is due to aluminum electromigration. Voids and hillock have been formed in aluminum metallization by high current density op- eration.
Fig.11 Voids and hillocks formation by Aluminum electromigration
5 SUMMARY
The Mitsubishi quality assurance system and examples of reliability control have been discussed. The customer's in- terests and requirements for high reliability IC & LSI are in- creasing significantly. To satisfy customer's expectancy.
Mitsubishi as an IC vendor, would like to make perpetual efforts in the following areas.
(1) Emphasis on built-in reliability at design stage and re- liability evaluation to investigate latent failure modes and acceleration factors.
(2) Execution of periodical endurance, environment and mechanical test to verify reliability target and realize higher reliability.
(3) Focus on development of advanced failure analysis techniques. Detail failure analysis, intensive corrective action and quick response to customer's analysis re- quest.
(4) Collection of customer's quality data in q,ualification, in- coming inspection, production and field use to improve PPM, fraction defective and FIT, failure rate.
Mitsubishi would highly appreciate if the customer would provide quality and reliability data of incoming inspection or field failure rate essential to verify and improve the quality/
reliability of IC & LSI.
• . MITSUBISHI
. . . . ELECTRIC
1-23MITSUBISHI MICROCOMPUTERS
PRECAUTIONS IN HANDLING MOS IC/LSls
A MaS transistor has a very thin oxide insulator under the gate electrode on the silicon substrate. It is operated by altering the conductance (gm) between source and drain to control mobile charges in the channel formed by the applied gate voltage.
If a high voltage were applied to a gate terminal, the insulator·film under the gate electrode could be destroyed, and all Mitsubishi MaS IC/lSls contain internal protection circuits at each input terminal to prevent this. It is inherent·
Iy necessary to apply reverse bias to the P·N junctions of a MaS IC/lSI.
Under certain conditions, however, it may be impossible to completely avoid destruction of the thin insulator-film due to the application of unexpectedly high voltage or thermal destruction due to excessive current from a forward biased P-N junction. Therefore the following recommendations should be followed in handling MaS devices.
1. KEEPING VOLTAGE AND CURRENT TO EACH TERMINAL BELOW MAXIMUM
RATINGS
1. The recommended ranges of operating conditions provide adequate safety margins. Operating within these limits will assure maximum equipment performance and quality.
2. Forward bias should not be applied to any terminal since excessive current may cause thermal destruction.
3. Output terminals should not be connected directly to the power supply. Short·circuiting of a terminal to a power supply having low impedance may cause burn·out of the internal leads or thermal destruction due to excessive current.
2. KEEPING ALL TERMINALS AT THE SAME POTENTIAL DURING TRANSPORT AND STORAGE
When MaS IC/lSls are not in use, both input and output terminals can be in a very high impedance state so that they are easily subjected to electrostatic induction from AC fields of the surrounding space or from charged objects in their vicinity. For this reason, MaS IC/lSls should be protected from electrostatic charges while being transported and stored by conductive rubber foam, aluminum foil, shielded boxes or other protective precautions.
3. KEEPING ELECTRICAL EQUIPMENT, WORK TABLES AND OPERATING
PERSONNEL AT THE SAME POTENTIAL
1. All electric equipment, work table surfaces and operat·
ing personnel should be grounded. Work tables should be covered with copper or aluminum plates of good conductivity, and ground~d. One method of grounding personnel, after making sure that there is no potential difference with electrical equipment, is by the use of a wristwatch metallic ring, etc. attached around the wrist and grounded in series with a 1M
n
resistor. Be sure that the grounding meets national. regulations on personnel safety.2. Current leakage from electric equipment must be prevented not only for personnel safety, but also to avert the destruction of MaS IC/lSls, as described above. Items such as testers, curve·tracers and synchro·
scopes must be checked for current leakage before being grounded.
4. PRECAUTIONS FOR MOUNTING OF MOS IC/LSls
1. The printed wiring lines between input and output ter- minals of MaS le/lSls should not be close to or parallel to high-voltage or high-power signal lines. Turning pow- er on while the device is short-circuited, either by a sol- der bridge made during assembly or by a probe during adjusting and testing, may cause maximum ratings to be exceeded, which can result in the destruction of the device.
2. When inputloutput, or input andlor output, terminals of MaS IC/lSls (now open·circuits) are connected, we must consider the possibility of current leakage and take precautions similar to §2 above. To reduce such undesirable trouble, it is recommended that an interface circuit be inserted at the input or output terminal, or a resistor with a resistance that does. not exceed the output driving capability of the MaS IC/lSI be inserted between the power supply and the ground.
3. A filter circuit should be inserted in the AC power supply line to absorb surges which can frequently be strong enough to destroy a MaS IC/lSI.
4. Terminal connections should be made as described in the catalog while being careful to meet specifications.
5. Ungrounded metal plates should not be placed near input or output terminals of any MaS IC/lSls, since destruction of the insulation may result if they become electrostatically charged.
6. Equipment cases should provide shielding from electro·
static charges for more reliable operation. When a plastic case is used, it. is desirable to coat the inside of the case with conductive paint and to ground it. This is considered necessary even for battery·operated equipment.
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