time, the memory (transfer destination) address is output to the address bus, and the R/IN signal goes Low to write data into memory. To receive the one bus cycle transfer
2-126
. • MITSUBI$HI
. . . . ELECTRIC
service for DMA purposes, however, the external circuitry must be formed in such a manner that the read and write signal inputs for I/O are the reversal of the M37720S1 FP's read and write signal outputs. Figure 53 shows the data transfer data flow of Figure 52.
When the address changes in forward direction, data 1 and data 2 are transferred to the I/O's 8 low-order bits and 8 high-order bits, respectively, in the first cycle of DMA transfer. In the next cycle of DMA transfer, data 3 and data 4 are transferred to the I/O's 8 low-order bits and 8 high-order bits, respectively. In this manner, the memory data are sequentially transferred to the I/O.
MITSUBISHIMICROCOMPUTERS
M37720S1FP,M37720S1AFP
16-BIT CMOS MICROCOMPUTER
If the address changes in backward direction, on the other hand, data 10 and data 9 are transferred to the 110's 8 high-order bits and 8 low-order bits, respectively, in the first DMA transfer cycle.
When one bus cycle transfer is effected in 16-bit units with an external bus width of 16 bits employed, as shown in Fi-gure 52, 16 bits of data are simultaneously read into the data bus. Therefore, determine the transfer start address so that transfer begins with an even-numbered address when the address change mode is forward or that transfer begins with an odd-numbered address when the address change mode is backward.
Read cycle
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M37720S1FP
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Fig.51 Two bus cycle transfer example
2-127
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DMAACKi
MITSUBISHI MICROCOMPUTERS
M37720S1FP,M37720S1AFP
Data bus high order Data bus low order
16-BIT CMOS MICROCOMPUTER
Internal clock ¢
E
Address
R/W
Data SLE SHE
.s-L..ILJ
--.J I
:=J(
Memory addressX 1'--_ _ _ _ _
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---~-_ ---~-_ ---~-_ ---~-_ --'1 , '
-When transfer is effected in 16-bit units with an external bus width of 16 bits employed
Fig.52 1 bus cycle transfer example(memory to 1/0)(1)
Even address -;, Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7 Data 8 Data 9 Data 10 Memory
Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7 Data 8 Data 9 Odd address -;. Data 10
Memory
Fig.53 Data flow at the date transfer
2-128
• MfTSUBISHl
"-ELECTRIC
Data eX) Low-order 8 bits
Data eX+l) High-order 8 bits lID
X= 1, 3, 5, 7 ... ·
X= 9, 7, 5, 3 ... ·
Data (Xl Low-order 8 bits
~---~
'--_ _ _ D_a_ta_eX_+_l_l _ _ _ _ ...J High-order 8 bits lID
MITSUBISHI MICROCOMPUTERS
M37720S1FP,M37720S1AFP
Figures 54 and 55 indicate the cases where transfer is made in 8-bit units with an external bus width of l6 bits employed.
Figure 54 shows the cases where an external bus width of 16 bits is employed with the 110 connected to the 8 low-order bits only. Connect the odd-numbered address memories to data bus high-order area (D8 - D15 ) and the even-numbered address memories to data bus low-order area (Do - D7) . When data is transferred from an odd-numbered memory address to 110, the data is read from the memory high-order to the data bus high-order. The read data first goes into the chip, is copied by the DMA controller to the data bus low-order, and then output out-side. Therefore, the data output to the data bus low-order is the same as that for the high-order. For !he 110, chip selec-tion is made according to the DMAACKI signal so that the data output to the data bus low-order is acquired. When data is transferred from an even-numbered a.ddress mem-ory to 110, the data read from the memmem-ory low-order is directly acquired by the 110. At this time, M37720S1 FP data bus pins Do to D7 are floating.
M 3 7 7 2
o
S 1 F p
Data flow of odd address
r - - - - ,
,
- - - Data bus high order
Data bus low order
Fig.54 1 bus cycle transfer example(memoly to 1/0)(2)
16-BIT CMOS MICROCOMPUTER
Internal clock ¢
Address JMemOry (odd) addressXMemory (even) addresK
IL ________________
~I"H" -R/W
Data bus high order Data bus low order
---~---~---~. ~
~
'---1
1 ' - - - - L
When transfer is effected in a-bit unils wilh an exlernal bus width of 16 bits employed and the I/O connected to a low-order bits only
2-129
MITSUBISHI MICROCOMPUTERS
M37720S1FP,M37720S1AFP
Figure 55 shows the case where the 110 is connected to the 8 high-order bits only. When data is transferred from an odd-numbered memory address to I/O, the data read from the memory high-order is directly acquired by the I/O. At this time, M37720S1 FP data bus pins 08 through 0'5 are floating. When data is transferred from an even-numbered memory address to 110, the data is read from the memory low-order to the data bus low-order. The read data first goes into the chip, is copied by the DMA controller to the data bus high-order, and then output outside. The I/O ac-quires that data. In one bus cycle transfer, data bus pin (Do - 07,08- 0,5 ) I/O changeover is automatically effected to initiate DMA transfer no matter whether the 8-bit I/O is connected to the low-or high-order of the data bus. In the above data copy between the chip's internal data buses, there is limitation on the transfer rate.
When one bus cycle transfer is effected with an external bus width of 8 bit, I/O connection selection bit must be "0".
When one bus cycle transfer is effected in 16-bit units with an external bus width of 16 bits employed, the following op-eration cannot be performed.
1. The object memory is DRAM, and an odd-numbered address designated as the first address for the backward transfer address change direction. Figure 56 shows the data bus status when one bus cycle transfer is made under the conditions indicated in Table 5.
Data ilow of even address