When bit 2 of the DMAi mode register is set to "1", the cy-cle steal transfer mode is selected. In the cycy-cle steal trans-fer mode, be sure to select the edge sense mode.
When the DMA request occurs in the cycle steal transfer mode, the DMA request flag is set to "1" as in the burst transfer mode. When the DMA request from a channel is accepted, DMA transfer starts. However, the DMA request flag is automatically cleared at the beginning of the first DMA transfer cycle. Therefore, if there is no channel DMA request at the end of one-unit transfer, the DMA controller returns the bus use right to the CPU. If there is a DMA re-quest from any channel, the DMA controller continues to use the bus and initiates DMA transfer for the channel. In the cycle steal transfer mode, the (3fiorities of the channels are considered at all times to assure that the DMA request from a channel having the highest priority is accepted to in-itiate DMA transfer execution. Transfer is effected in one transfer unit segments. However, the DMA permission bit will not be cleared even if the DMA request flag is cleared.
Therefore, when the DMA request flag is set to "1", transfer is resumed at the point of interruption. When the transfer counter value is "0" in normal transfer, or both of the trans-fer counter and transtrans-fer block counter value is "0" in array chain transfer, the DMA permission bit is cleared to termin-ate the whole DMA transfer operation.
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Figure 59 shows an example of cycle steal transfer. When the DMAREQi pin input changes from "H" to "L", the DMA1 request flag is set to "1" and the DMA controller acquires the bus use right to initiate DMA transfer. The DMA 1 re-quest flag is cleared when the channel 1 transfer cycle starts. Therefore, if there is no DMA transfer request from the other channels, the DMA controller returns the bus use right to the CPU at the end of one transfer cycle. In the ex-ample showed in Figure 59, however, DMAO transfer cycle execution continues because the channel
a
request flag is set to "1 ". When the DMAO transfer cycle is terminated, the DMA request flags of all channels are set to "0" so that the DMA controller returns the bus use right to the CPU. When the DMA1 request flag is set to "1", only one cycle of trans-fer operation is performed. Even if the DMA1 request flag is cleared at this time, the DMA1 request flag is set to "1 "again to effect continued transfer as long as the DMAREQi pin input goes Low before the end of the next transfer cy-cle. In cycle steal transfer, the priorities of individual chan-nels are examined at the end of each transfer cycle. There-fore, if the request is .sent from channel 0, which has a higher priority than channel 1, channel
a
transfer is ex-ecuted first. Further, if the refresh request is sent from the DRAM controller, such a request for. bus use takes prece-dence as it has a high priority.Refresh cycle DRAM refresh
c-=- =- -=--=---=--=- -=- -=- =: = =- =- ~ -=---- -=- =- = =: R : =: -=- ~ ~ .=- -=- -=- -=- -=- -=--=- -=- J
r---+-~---,
L _ _ _ _ _ _ _ _ _ _ _ _ _ _ ~ _ _ _ _ _ _ _ _ _ ~-~---J
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h
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i'. L , " '" One transfer cycle ~ '" y'
r - - - i - ,
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---~-~L---.J-f--_I_ . .
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I I ' 1
DMARE01 DMA 1 request flag
:
DMAREOO LDr---~LJ
! ,
DMAO request flagJ _ _ _ _
...J'H n
L _ _ _ _ _ _ _ ...,.... _ _ _ _ _ _ _ Refresh request________________________ --Jn
L _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _Fig.59 Cycle steal transfer example
2-135
I
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Priority
Priorities are assigned to all DMA channels. Either the fixed or rotative priority can be selected. When bit 0 (priority selection bit) of the DMAC control register is set to "0", the fixed priorityis selected. Note that the fixed priority is auto-matically chosen upon resetting. In the fixed priority, the channels are given fixed priorities and DMA transfer is ex-ecuted in the order of priority. From high to low, the priori-ties are assigned to channels 0, 1, 2, and 3. As indicated in Figure 61, the priorities are checked when the first DMA request is received in the burst transfer mode or at each cycle end in the cycle steal transfer mode.
When bit 0 of the DMAC control register is set to "1 ", the
(1) Before the start of transfer (after resetting)
Channel 0
:>
Channell:>
(2) After completion of channel 0 transfer
16·BIT CMOS MICROCOMPUTER
rotative priority is used. From high to low, the initial priori-ties are assigned to channels 0, 1, 2, and 3 as is the case with the fixed priority. When the DMAtransfer for one chan-nel is normally terminated with the rotative priority em-ployed, the priorities are rotated in such a manner that the channel, for which transfer has just been completed, has the lowest priority. For example, when channel 0 transfer is normally terminated as shown in Figure 60, the priorities are rotated upon completion of transfer so that the new priorities are, in decreasing order, channel 1, channel 2, channel 3, and channel O.Thepriorities remain unchanged when DMA transfer is forcibly terminated by TC pin input or.
DMA permission bit clearing.
Channel 2
::>
Channel 3II
Channel 0I~I
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Channel 2I
E Channel 3I I
0
Channell
.>
Channel 2.>
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Channel 0(3) After completion of channel 2 transfer
[I
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Channel 2 ~ Channel 3I~·I
Channel 0b
<>
Channel 3
:>
Channel 0:>
Channell:>
Channel 2Flg.60 Rotative priority
2-136
MITSUBISHI MICROCOMPUTERS
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16-BIT CMOS MICROCOMPUTER
DRAM relresh
r---~
~---~
'fchannel number
[======_1 11 11 11 [-I 11 I 1 11 11 11 1_==-... 1....,.1-0 ... 1-0 .... 1-o ... l....;o!...,...,11
DMA controller
CPU L..-_ _ _ _
..J[:::::::: =====:::::::::: ::::=::::::== .... 1_---1[:::: :::::::J
Priority determination
t t
among DMA c h a n n e l - - - + I - - - I ,
DMAO request Ilag
---4!.~-...J +
DMAl request Ilag _ _ _ _ ---IIr-
.f',~---_:.. __
~~~---+ +
DMA2 request Ilag _ _ _ _ ---I
i I
I
~DMA3 requestllag _ _ _ _ _ ~~~---...J
DRAM relresh
Priority resolution at burst transfer mode
~-:.~ -_-_-_ _=_ -:. __ -_--:.-=--=--=--=-~D== =-=== =- == == -= == ====J
c::: :::::. -::.::.::::::::: :::.::-.::- .:---t-f,::-.::-.:.::-.::-::.::.::. ::.::. -::. -::.-::.---.:~:?~~, ""mO.,
[=:::::==::11112101
113 [] 011121310131 ==-] 111211
DMA controller
t ~ t
.---'1 =- =- =- =-=- -=--_-_-_-_-____ _=_ =-::::~=-] 1 =-~~=J
CPU
Priority determination
!.t' 1
:I:t t
:I::I: :I: ! t :I:!
!' ~ ~among DMA channel---++--~+--I--+-+--!-...j----<+f__+.j.-+.j.-+.j.-+_-.j.f_~.j.---+.j.--.j.j_~i
i i~! !,~l i i i 1 i i i i !
DMAO request Ilag
,_--+--+ -++1 r4-4i ' ~ + ~ +r'T1 + + + + +
N ' i ~ * j ! I~ i ! I i ! ~' I '
DMAl request I l a g _ _ _ _ _
I.J.. I I ~ 1 1 1 1 I
DMA2 request Ilag
,_---'I ' + ~. ,! + I, T + + r r ~I ~ ' " r T + + _ + r rI I I, ~ ~ ,!
1 1 ~ ~ ~ i i, l ~ ku i I : i
DMA3 request
Ilag,---~e---4e~1 ~ ~
-'1 .9 ~ ~ ~
Priority resolution at cycle steal transfer mode
@ :
Channel having the highest priority Fig,61 Channel priority determination timing (Fixed priority)2-137